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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
Table 6-58. Timing Requirements for McBSP0 [1.0V]
NO.
2
t
Cycle time, CLKR/X
c(CKRX)
3
t
Pulse duration, CLKR/X high or CLKR/X low
w(CKRX)
5
t
Setup time, external FSR high before CLKR low
su(FRH-CKRL)
6
t
Hold time, external FSR high after CLKR low
h(CKRL-FRH)
7
t
Setup time, DR valid before CLKR low
su(DRV-CKRL)
8
t
Hold time, DR valid after CLKR low
h(CKRL-DRV)
10
t
Setup time, external FSX high before CLKX low
su(FXH-CKXL)
11
t
Hold time, external FSX high after CLKX low
h(CKXL-FXH)
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
144
Peripheral Information and Electrical Specifications
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AM1808
(1)
(see
Figure
6-32)
1.0V
MIN
(2) (3)
CLKR/X ext
2P or 26.6
(4)
CLKR/X ext
P - 1
CLKR int
20
CLKR ext
5
CLKR int
6
CLKR ext
3
CLKR int
20
CLKR ext
5
CLKR int
3
CLKR ext
3
CLKX int
20
CLKX ext
5
CLKX int
6
CLKX ext
3
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UNIT
MAX
ns
ns
ns
ns
ns
ns
ns
ns
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