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Table 6-78. Additional
NO.
Delay from slave
assertion of
17
t
SPI1_ENA active to
d(EN A_SPC)M
first SPI1_CLK from
(4)
master.
Max delay for slave to
deassert SPI1_ENA
after final SPI1_CLK
18
t
d(SPC_ENA)M
edge to ensure
master does not begin from SPI1_CLK rising
the next transfer.
(1) These parameters are in addition to the general timings for SPI master modes
(2) P = SYSCLK2 period; M = t
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
Table 6-79. Additional
NO.
PARAMETER
Delay from
SPI1_SCS active
19
t
d(SCS_SPC)M
to first
SPI1_CLK
Delay from final
SPI1_CLK edge to from SPI1_CLK falling
20
t
master
d(SPC_SCS)M
deasserting
SPI1_SCS
(1) These parameters are in addition to the general timings for SPI master modes
(2) P = SYSCLK2 period; M = t
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
Copyright © 2010–2014, Texas Instruments Incorporated
(1)
SPI1 Master Timings, 4-Pin Enable Option
PARAMETER
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
(5)
Polarity = 1, Phase = 1,
from SPI1_CLK rising
(SPI master bit clock period)
c(SPC)M
(1)
SPI1 Master Timings, 4-Pin Chip Select Option
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
(4) (5)
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
Polarity = 1, Phase = 0,
from SPI1_CLK rising
(6) (7)
Polarity = 1, Phase = 1,
from SPI1_CLK rising
(SPI master bit clock period)
c(SPC)M
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SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
1.3V, 1.2V
1.1V
MIN
MAX
MIN
3P+5
0.5M+3P+5
0.5M+3P+5
3P+5
0.5M+3P+5
0.5M+3P+5
0.5M+P+5
0.5M+P+5
P+5
0.5M+P+5
0.5M+P+5
P+5
(Table
6-76).
1.3V, 1.2V
1.1V
MIN
MAX
MIN
2P-1
2P-5
0.5M+2P-1
0.5M+2P-5
2P-1
2P-5
0.5M+2P-1
0.5M+2P-5
0.5M+P-1
0.5M+P-5
P-1
P-5
0.5M+P-1
0.5M+P-5
P-1
P-5
(Table
6-76).
Peripheral Information and Electrical Specifications
AM1808
AM1808
(2) (3)
1.0V
UNIT
MAX
MIN
MAX
3P+5
3P+6
0.5M+3P+6
3P+5
3P+6
0.5M+3P+6
0.5M+P+6
P+5
P+6
0.5M+P+6
P+5
P+6
(2) (3)
1.0V
UNIT
MAX
MIN
MAX
2P-6
0.5M+2P-6
2P-6
0.5M+2P-6
0.5M+P-6
P-6
0.5M+P-6
P-6
ns
ns
ns
ns
163
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