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Table 6-76. General Timing Requirements for SPI1 Master Modes
NO.
1
t
Cycle Time, SPI1_CLK, All Master Modes
c(SPC)M
2
t
Pulse Width High, SPI1_CLK, All Master Modes
w(SPCH)M
3
t
Pulse Width Low, SPI1_CLK, All Master Modes
w(SPCL)M
Delay, initial data bit valid on
4
t
SPI1_SIMO to initial edge on
d(SIMO_SPC)M
(3)
SPI1_CLK
Delay, subsequent bits valid on from SPI1_CLK falling
5
t
SPI1_SIMO after transmit edge
d(SPC_SIMO)M
of SPI1_CLK
Output hold time, SPI1_SIMO
6
t
valid after receive edge of
oh(SPC_SIMO)M
SPI1_CLK
Input Setup Time, SPI1_SOMI
7
t
valid before receive edge of
su(SOMI_SPC)M
SPI1_CLK
Input Hold Time, SPI1_SOMI
8
t
valid after receive edge of
ih(SPC_SOMI)M
SPI1_CLK
(1) P = SYSCLK2 period; M = t
(2) This timing is limited by the timing shown or 3P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.
Copyright © 2010–2014, Texas Instruments Incorporated
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK rising
Polarity = 0, Phase = 1,
Polarity = 1, Phase = 0,
from SPI1_CLK falling
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
Polarity = 0, Phase = 0,
to SPI1_CLK falling
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK rising
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
(SPI master bit clock period)
c(SPC)M
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SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
1.3V, 1.2V
1.1V
MIN
MAX
MIN
(2)
(2)
20
256P
30
0.5M-1
0.5M-1
0.5M-1
0.5M-1
5
-0.5M+5
-0.5M+5
5
-0.5M+5
-0.5M+5
5
5
5
5
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
4
5
4
5
4
5
4
5
Peripheral Information and Electrical Specifications
AM1808
AM1808
(1)
1.0V
UNIT
MAX
MIN
MAX
(2)
256P
40
256P
ns
0.5M-1
ns
0.5M-1
ns
5
6
-0.5M+6
ns
5
6
-0.5M+6
5
6
5
6
ns
5
6
5
6
0.5M-3
0.5M-3
ns
0.5M-3
0.5M-3
1.5
1.5
ns
1.5
1.5
6
6
ns
6
6
161
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