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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
UHPI_HCS
(D)
UHPI_HAS
1
UHPI_HCNTL[1:0]
1
UHPI_HR/W
1
UHPI_HHWIL
(A)(C)
UHPI_HSTROBE
UHPI_HD[15:0]
(input)
(B)
UHPI_HRDY
A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1 XOR HDS2)] OR
UHPI_HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the
state of the FIFO, transitions on UHPI_HRDY may or may not occur.
C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2. UHPI_HCS
timing requirements are reflected by parameters for UHPI_HSTROBE.
D
The diagram above assumes UHPI_HAS has been pulled high.
216
Peripheral Information and Electrical Specifications
2
2
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3
5
Figure 6-67. UHPI Write Timing (HAS Not Used, Tied High)
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2nd Half-Word
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