Texas Instruments AM1808 User Manual page 255

www.ti.com
BIT NAME
31:28 VARIANT
27:12 PART NUMBER
11-1 MANUFACTURER
0 LSB
6.34.4.2 JTAG Test-Port Electrical Data/Timing
Table 6-147. Timing Requirements for JTAG Test Port (see
No.
1 t Cycle time, TCK
c(TCK)
2 t Pulse duration, TCK high
w(TCKH)
3 t Pulse duration, TCK low
w(TCKL)
4 t Cycle time, RTCK
c(RTCK)
5 t Pulse duration, RTCK high
w(RTCKH)
6 t Pulse duration, RTCK low
w(RTCKL)
7 t Setup time, TDI/TMS/TRST valid before RTCK high
su(TDIV-RTCKH)
8 t Hold time, TDI/TMS/TRST valid after RTCK high
h(RTCKH-TDIV)
Table 6-148. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
No.
9 t Delay time, RTCK low to TDO valid
d(RTCKL-TDOV)
TCK
RTCK
TDO
TDI/TMS/TRST
6.34.5 JTAG 1149.1 Boundary Scan Considerations
To use boundary scan, the following sequence should be followed:
• Execute a valid reset sequence and exit reset
• Wait at least 6000 OSCIN clock cycles
• Enter boundary scan mode using the JTAG pins
No specific value is required on the EMU0 and EMU1 pins for boundary scan testing. If TRST is not driven
by the boundary scan tool or tester, TRST should be externally pulled high during boundary scan testing.
Copyright © 2010–2014, Texas Instruments Incorporated
Table 6-146. JTAG ID Register Selection Bit Descriptions
Variant (4-Bit) value
Part Number (16-Bit) value
Manufacturer (11-Bit) value
LSB. This bit is read as a "1".
(see
PARAMETER
1
2
4
5
9
8
7
Figure 6-89. JTAG Test-Port Timing
Submit Documentation Feedback
Product Folder Links:
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
DESCRIPTION
1.3V, 1.2V
MIN MAX
40
16
16
40
16
16
4
4
Figure 6-89)
1.3V, 1.2V
MIN MAX
18
3
6
Peripheral Information and Electrical Specifications
AM1808
AM1808
Figure 6-89)
1.1V 1.0V
MIN MAX MIN MAX
50 66.6
20 26.6
20 26.6
50 66.6
20 26.6
20 26.6
4 4
6 8
1.1V 1.0V
MIN MAX MIN MAX
23 31
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
ns
255