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SIGNAL
NAME
DDR_DQM[0]
DDR_DQM[1]
DDR_DQS[0]
DDR_DQS[1]
DDR_BA[2]
DDR_BA[1]
DDR_BA[0]
DDR_DQGATE0
DDR_DQGATE1
DDR_ZP
DDR_VREF
DDR_DVDD18
Copyright © 2010–2014, Texas Instruments Incorporated
Table 3-8. DDR2/mDDR Terminal Functions (continued)
NO.
W13
R10
T14
V11
U8
T9
V8
R11
R12
U12
R6
N10, P10, N9,
P9, R9, P8,
R8, P7, R7,
N6
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SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
(1)
(2)
TYPE
PULL
O
IPD
DDR2 data mask outputs
O
IPD
I/O
IPD
DDR2 data strobe inputs/outputs
I/O
IPD
O
IPD
O
IPD
DDR2 SDRAM bank address
O
IPD
DDR2 loopback signal for external DQS gating.
O
IPD
Route to DDR and back to DDR_DQGATE1 with
same constraints as used for DDR clock and data.
DDR2 loopback signal for external DQS gating.
I
IPD
Route to DDR and back to DDR_DQGATE0 with
same constraints as used for DDR clock and data.
DDR2 reference output for drive strength calibration
O
—
of N and P channel outputs. Tie to ground via 50
ohm resistor @ 5% tolerance.
DDR voltage input for the DDR2/mDDR I/O buffers.
I
—
Note even in the case of mDDR an external resistor
divider connected to this pin is necessary.
PWR
—
DDR PHY 1.8V power supply pins
AM1808
AM1808
DESCRIPTION
Device Overview
25
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