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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
3.5
Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings.
3.5.1 Pin Map (Bottom View)
The following graphics show the bottom view of the ZCE and ZWT packages pin assignments in four
quadrants (A, B, C, and D). The pin assignments for both packages are identical.
1
2
VP_DOUT[0]/
VP_DOUT[1]/
LCD_D[0]/
LCD_D[1]/
W
UPP_XD[8]/
UPP_XD[9]/
GP7[8]/
GP7[9]/
PRU1_R31[8]
PRU1_R31[9]
VP_DOUT[3]/
VP_DOUT[4]/
LCD_D[3]/
LCD_D[4]/
V
UPP_XD[11]/
UPP_XD[12]/
GP7[11]/
GP7[12]/
PRU1_R31[11]
PRU1_R31[12]
VP_DOUT[6]/
VP_DOUT[7]/
LCD_D[6]/
LCD_D[7]/
U
UPP_XD[14]/
UPP_XD[15]/
GP7[14]/
GP7[15]/
PRU1_R31[14]
PRU1_R31[15]
VP_DOUT[9]/
VP_DOUT[10]/
LCD_D[9]/
LCD_D[10]/
UPP_XD[1]/
UPP_XD[2]/
T
GP7[1]/
GP7[2]/
BOOT[1]
BOOT[2]
VP_DOUT[12]/
VP_DOUT[13]/
LCD_D[12]/
LCD_D[13]/
UPP_XD[4]/
UPP_XD[5]/
R
GP7[4]/
GP7[5]/
BOOT[4]
BOOT[5]
SATA_VDD
SATA_VDD
P
SATA_REFCLKN
SATA_REFCLKP
N
SATA_VSS
SATA_VDD
M
SATA_RXP
L
SATA_RXN
MMCSD1_DAT[2]/
SATA_VSS
SATA_VSS
K
1
2
14
Device Overview
3
4
5
VP_DOUT[2]/
LCD_D[2]/
DDR_A[10]
DDR_A[6]
UPP_XD[10]/
GP7[10]/
PRU1_R31[10]
VP_DOUT[5]/
LCD_D[5]/
DDR_A[12]
DDR_A[5]
UPP_XD[13]/
GP7[13]/
PRU1_R31[13]
VP_DOUT[8]/
LCD_D[8]/
UPP_XD[0]/
DDR_A[8]
DDR_A[4]
GP7[0]/
BOOT[0]
VP_DOUT[11]/
LCD_D[11]/
UPP_XD[3]/
DDR_A[11]
DDR_A[13]
GP7[3]/
BOOT[3]
VP_DOUT[14]/
LCD_D[14]/
LCD_AC_ENB_CS/
UPP_XD[6]/
DVDD3318_C
GP6[0]/
GP7[6]/
PRU1_R31[28]
BOOT[6]
VP_DOUT[15]/
LCD_D[15]/
SATA_VDDR
UPP_XD[7]/
DVDD3318_C
GP7[7]/
BOOT[7]
SATA_REG
SATA_VDD
V
SS
V
V
NC_M3
SS
SS
SATA_VSS
DV
V
DD3318_C
SS
VP_CLKOUT2/
VP_CLKOUT3/
PRU1_R30[0]/
PRU1_R30[2]/
DV
DD18
GP6[1]/
GP6[3]/
PRU1_R31[1]
PRU1_R31[3]
3
4
5
Figure 3-1. Pin Map (Quad A)
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6
7
8
DDR_A[2]
DDR_CLKN
DDR_CLKP
DDR_A[3]
DDR_CKE
DDR_BA[0]
DDR_A[7]
DDR_A[0]
DDR_BA[2]
DDR_A[9]
DDR_A[1]
DDR_WE
DDR_VREF
DDR_DVDD18
DDR_DVDD18
DVDD3318_C
DDR_DVDD18
DDR_DVDD18
DDR_DVDD18
RV
CV
DD
DD
V
V
CV
SS
SS
DD
DV
V
V
DD18
SS
SS
V
V
SS
SS
CV
DD
6
7
8
Copyright © 2010–2014, Texas Instruments Incorporated
AM1808
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9
10
DDR_D[15]
DDR_RAS
W
DDR_D[13]
V
DDR_CS
U
DDR_CAS
DDR_D[12]
DDR_BA[1]
DDR_D[10]
T
DDR_DVDD18
DDR_DQM[1]
R
DDR_DVDD18
DDR_DVDD18
P
DDR_DVDD18
DDR_DVDD18
N
CV
V
DD
SS
M
V
V
L
SS
SS
V
V
SS
SS
K
9
10
A
B
D
C
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