Texas Instruments Sitara AM1335 Series Manual
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Texas Instruments Sitara AM1335 Series Manual

Arm cortex-a8 (mpus)
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Sitara™ AM335x ARM
Cortex™-A8
Microprocessors (MPUs)

Silicon Revisions 2.1, 2.0, 1.0

Silicon Errata
Literature Number: SPRZ360F
October 2011 – Revised November 2013

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Summary of Contents for Texas Instruments Sitara AM1335 Series

  • Page 1: Silicon Revisions

    ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) Silicon Revisions 2.1, 2.0, 1.0 Silicon Errata Literature Number: SPRZ360F October 2011 – Revised November 2013...

  • Page 2: Table Of Contents

    OSC1: RTC_XTALIN Terminal Has an Internal Pull-up Resistor When OSC1 is Disabled ............Known Design Exceptions to Functional Specifications ......................... Revision History Table of Contents SPRZ360F – October 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...

  • Page 3: Introduction

    Predictions show that prototype devices (X or P) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

  • Page 4: Revision Identification

    (J) On some "X" devices, the device speed may not be shown. ® SPRZ360F – October 2011 – Revised November 2013 Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Revision 2.1, 2.0, 1.0) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 5 REVISION REVISION r3p2 0000 22.02 r3p2 0001 22.03 r3p2 0010 22.03 SPRZ360F – October 2011 – Revised November 2013 ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Submit Documentation Feedback Revision 2.1, 2.0, 1.0) Copyright © 2011–2013, Texas Instruments Incorporated...

  • Page 6: All Errata Listed With Silicon Revision Number

    ARM Cortex-A8: OPP50 Operation on MPU Domain Not Advisory 1.0.15 Supported ® SPRZ360F – October 2011 – Revised November 2013 Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Revision 2.1, 2.0, 1.0) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 7 EMU0 and EMU1: Terminals Must Be Pulled High Before Advisory 1.0.36 ICEPick Samples SPRZ360F – October 2011 – Revised November 2013 ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Submit Documentation Feedback Revision 2.1, 2.0, 1.0) Copyright © 2011–2013, Texas Instruments Incorporated...

  • Page 8: Usage Notes And Known Design Exceptions To Functional Specifications

    0x2 field in the PMCR), the SR_TIM value in the PMCR must to be programmed to a value greater than or equal to 0x9. ® SPRZ360F – October 2011 – Revised November 2013 Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Revision 2.1, 2.0, 1.0) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...

  • Page 9: Boot: Usb Boot Rom Code Uses Default Datapolarity

    2-to-1 multiplexer IO power supply domains may need to operate at the same voltage since they share common signals. SPRZ360F – October 2011 – Revised November 2013 ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Submit Documentation Feedback Revision 2.1, 2.0, 1.0) Copyright © 2011–2013, Texas Instruments Incorporated...

  • Page 10: Pin Multiplexing: Valid Io Sets And Restrictions

    IO Sets, are valid due to timing limitations. These valid IO Sets were carefully chosen to provide many possible application scenarios for the user. ® Texas Instruments has developed a Windows -based application called Pin Mux Utility that helps a system designer select the appropriate pin-multiplexing configuration for their AM335x-based product design.

  • Page 11: Osc1: Rtc_Xtalin Terminal Has An Internal Pull-Up Resistor When Osc1 Is Disabled

    The current recommendation is to remove any external pull-down resistor from the RTC_XTALIN terminal and leave this terminal open-circuit when not using OSC1. SPRZ360F – October 2011 – Revised November 2013 ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Submit Documentation Feedback Revision 2.1, 2.0, 1.0) Copyright © 2011–2013, Texas Instruments Incorporated...

  • Page 12: Known Design Exceptions To Functional Specifications

    Do not configure the AM335x EMU[1:0] pins to operate as GPIO if you need to export Workarounds trace messages. ® SPRZ360F – October 2011 – Revised November 2013 Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Revision 2.1, 2.0, 1.0) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 13 Use an active high interrupt source or use an external inverter to change the polarity of Workarounds any active low interrupt source. SPRZ360F – October 2011 – Revised November 2013 ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Submit Documentation Feedback Revision 2.1, 2.0, 1.0) Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 14 BOOTP packet from a MAC address on the host's list. ® SPRZ360F – October 2011 – Revised November 2013 Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Revision 2.1, 2.0, 1.0) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 15 Clear the timer capture interrupt by writing 1 to the TCAR_IT_FLAG bit of the respective IRQSTATUS register. SPRZ360F – October 2011 – Revised November 2013 ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Submit Documentation Feedback Revision 2.1, 2.0, 1.0) Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 16 Enable the desired CPSW interrupts in the C0_xx_EN field in the respective C0_RX_EN/C0_TX_EN register. ® SPRZ360F – October 2011 – Revised November 2013 Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Revision 2.1, 2.0, 1.0) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 17 A complete timing analysis is required to determine the optimum delay of each PCB signal trace. SPRZ360F – October 2011 – Revised November 2013 ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Submit Documentation Feedback Revision 2.1, 2.0, 1.0) Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 18 Workarounds TX_THRESHOLD + TRIGGER_LEVEL ≤ 63 (TX FIFO Size - 1). ® SPRZ360F – October 2011 – Revised November 2013 Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Revision 2.1, 2.0, 1.0) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 19 Operating in USB device mode - There is no workaround for this mode of operation. SPRZ360F – October 2011 – Revised November 2013 ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Submit Documentation Feedback Revision 2.1, 2.0, 1.0) Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 20 CONF_MDIO 0x44E1_0948 CONF_MDC 0x44E1_094C Re-initialize these registers after exiting DeepSleep0. Workarounds ® SPRZ360F – October 2011 – Revised November 2013 Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Revision 2.1, 2.0, 1.0) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 21 1b. RMII2_REFCLK can be configured to input mode by setting bit 7 of the GMII_SEL register to 1b. SPRZ360F – October 2011 – Revised November 2013 ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Submit Documentation Feedback Revision 2.1, 2.0, 1.0) Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 22 Therefore, the ROM code must never be configured such that it attempts to boot from RMII. Use MII if Ethernet boot is required. Workarounds ® SPRZ360F – October 2011 – Revised November 2013 Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Revision 2.1, 2.0, 1.0) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 23 SPRZ360F – October 2011 – Revised November 2013 ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Submit Documentation Feedback Revision 2.1, 2.0, 1.0) Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 24 VDD_MPU configured for any valid OPP greater than OPP100. There is no workaround for this issue. Workarounds ® SPRZ360F – October 2011 – Revised November 2013 Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Revision 2.1, 2.0, 1.0) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 25 The Reset Isolation feature is not enabled by default. There is no workaround for this issue. Workarounds SPRZ360F – October 2011 – Revised November 2013 ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Submit Documentation Feedback Revision 2.1, 2.0, 1.0) Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 26 ARM (A8), L3, L4, and the respective DDR clocks at the reduced frequencies defined by OPP50. ® SPRZ360F – October 2011 – Revised November 2013 Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Revision 2.1, 2.0, 1.0) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 27 Ethernet, the switch would be returned to its normal operating mode before the MMC0 boot code is updated. SPRZ360F – October 2011 – Revised November 2013 ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Submit Documentation Feedback Revision 2.1, 2.0, 1.0) Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 28 Figure ® SPRZ360F – October 2011 – Revised November 2013 Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Revision 2.1, 2.0, 1.0) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 29 200 µA Maximum high-level input 6600 current up to 100 µA SPRZ360F – October 2011 – Revised November 2013 ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Submit Documentation Feedback Revision 2.1, 2.0, 1.0) Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 30 The LCD panel input would need a pull-up or pull-down resistor to force an inactive state while the switch is open. ® SPRZ360F – October 2011 – Revised November 2013 Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Revision 2.1, 2.0, 1.0) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 31 Table 7. Latch-up Performance Limits - Silicon Revisions 1.0 and 2.0 PARAMETER UNITS Latch-up Performance Class II (105°C) Not applicable. Workarounds SPRZ360F – October 2011 – Revised November 2013 ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Submit Documentation Feedback Revision 2.1, 2.0, 1.0) Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 32 Figure 5. TSC Generates False Pen-up Interrupt There are two possible workarounds for this problem: Workarounds ® SPRZ360F – October 2011 – Revised November 2013 Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Revision 2.1, 2.0, 1.0) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 33 FIFO. You will need to set the Step_ID_tag bit in the CTRL register so that you can identify the garbage result in the FIFO and discard it. SPRZ360F – October 2011 – Revised November 2013 ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Submit Documentation Feedback Revision 2.1, 2.0, 1.0) Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 34 Rseries_max = [(ADC_ClkDiv + 1) *( SampleDelay + 2) / (116 x 10 ) * (CLK_M_OSC)] - 200 Ω - Rsource_max ® SPRZ360F – October 2011 – Revised November 2013 Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Revision 2.1, 2.0, 1.0) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 35 / 50 Ω] = 37.8 mA while the typical current requirement for these sources during normal operation would be about 90 uA. SPRZ360F – October 2011 – Revised November 2013 ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Submit Documentation Feedback Revision 2.1, 2.0, 1.0) Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 36 USB2PHY register access followed by a USB subsystem soft reset followed by another USB2PHY register access. ® SPRZ360F – October 2011 – Revised November 2013 Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Revision 2.1, 2.0, 1.0) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
  • Page 37 190 ns after the falling edge of WARMRSTn. SPRZ360F – October 2011 – Revised November 2013 ® Sitara™ AM335x ARM Cortex™-A8 Microprocessors (MPUs) (Silicon Submit Documentation Feedback Revision 2.1, 2.0, 1.0) Copyright © 2011–2013, Texas Instruments Incorporated...

  • Page 38: Revision History

    1.0.36, EMU0 and EMU1: Terminals Must Be Pulled High Before ICEPick Samples NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Revision History SPRZ360F – October 2011 – Revised November 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...

  • Page 39: Important Notice

    IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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