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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
Table 6-77. General Timing Requirements for SPI1 Slave Modes
NO.
9
t
Cycle Time, SPI1_CLK, All Slave Modes
c(SPC)S
10
t
Pulse Width High, SPI1_CLK, All Slave Modes
w(SPCH)S
11
t
Pulse Width Low, SPI1_CLK, All Slave Modes
w(SPCL)S
Setup time, transmit data
written to SPI before initial
12
t
su(SOMI_SPC)S
clock edge from
(3) (4)
master.
Delay, subsequent bits valid
13
t
on SPI1_SOMI after transmit
d(SPC_SOMI)S
edge of SPI1_CLK
Output hold time, SPI1_SOMI
14
t
valid after receive edge of
oh(SPC_SOMI)S
SPI1_CLK
Input Setup Time, SPI1_SIMO to SPI1_CLK rising
15
t
valid before receive edge of
su(SIMO_SPC)S
SPI1_CLK
Input Hold Time, SPI1_SIMO
16
t
valid after receive edge of
ih(SPC_SIMO)S
SPI1_CLK
(1) P = SYSCLK2 period; S = t
(2) This timing is limited by the timing shown or 3P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.
(4) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
162
Peripheral Information and Electrical Specifications
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK rising
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK falling
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
Polarity = 0, Phase = 0,
to SPI1_CLK falling
Polarity = 0, Phase = 1,
Polarity = 1, Phase = 0,
to SPI1_CLK rising
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
(SPI slave bit clock period)
c(SPC)S
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1.3V, 1.2V
1.1V
MIN
MAX
MIN
(2)
(2)
40
50
18
22
18
22
2P
2P
2P
2P
2P
2P
2P
2P
15
15
15
15
0.5S-4
0.5S-10
0.5S-4
0.5S-10
0.5S-4
0.5S-10
0.5S-4
0.5S-10
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
4
5
4
5
4
5
4
5
Copyright © 2010–2014, Texas Instruments Incorporated
AM1808
www.ti.com
(1)
1.0V
UNIT
MAX
MIN
MAX
(2)
60
ns
27
ns
27
ns
2P
2P
ns
2P
2P
17
19
17
19
ns
17
19
17
19
0.5S-12
0.5S-12
ns
0.5S-12
0.5S-12
1.5
1.5
ns
1.5
1.5
6
6
ns
6
6
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