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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
NO.
Delay from final clock receive
edge on SPI0_CLK to slave 3-
30
t
dis(SPC_ENA)S
stating or driving high
(4)
SPI0_ENA.
(4) SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor should
be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.
160
Peripheral Information and Electrical Specifications
Table 6-75. Additional SPI0 Slave Timings, 5-Pin Option
PARAMETER
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
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(1)(2)(3)
(continued)
1.3V, 1.2V
1.1V
MIN
MAX
MIN
2.5P+17.5
2.5P+17.5
2.5P+17.5
2.5P+17.5
AM1808
1.0V
MAX
MIN
MAX
2.5P+20
2.5P+27
2.5P+20
2.5P+27
2.5P+20
2.5P+27
2.5P+20
2.5P+27
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UNIT
ns
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