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Table 6-4. Allowed PLL Operating Conditions (PLL0 and PLL1)
NO
PARAMETER
.
1
PLLRST: Assertion time during initialization
Lock time: The time that the application has to wait for
2
the PLL to acquire lock before setting PLLEN, after
changing PREDIV, PLLM, or OSCIN
3
PREDIV: Pre-divider value
4
PLLREF: PLL input frequency
5
PLLM: PLL multiplier values
6
PLLOUT: PLL output frequency
7
POSTDIV: Post-divider value
(1) The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 300 and 600 MHz, but the frequency
going into the SYSCLK dividers (after the post divider) cannot exceed the maximum clock frequency defined for the device at a given
voltage operating point.
6.6.2 Device Clock Generation
PLL0 is controlled by PLL Controller 0 and PLL1 is controlled by PLL Controller 1. PLLC0 and PLLC1
manage the clock ratios, alignment, and gating for the system clocks to the chip. The PLLCs are
responsible for controlling all modes of the PLL through software, in terms of pre-division of the clock
inputs (PLLC0 only), multiply factors within the PLLs, and post-division for each of the chip-level clocks
from the PLLs outputs. PLLC0 also controls reset propagation through the chip, clock alignment, and test
points.
PLLC0 provides clocks for the majority of the system but PLLC1 provides clocks to the mDDR/DDR2
Controller and the ASYNC3 clock domain to provide frequency scaling immunity to a defined set or
peripherals. The ASYNC3 clock domain can either derive its clock from PLL1_SYSCLK2 (for frequency
scaling immunity from PLL0) or from PLL0_SYSCLK2 (for synchronous timing with PLL0) depending on
the application requirements. In addition, some peripherals have specific clock options independent of the
ASYNC clock domain.
6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)
The processor supports multiple operating points by scaling voltage and frequency to minimize power
consumption for a given level of processor performance.
Frequency scaling is achieved by modifying the setting of the PLL controllers' multipliers, post-dividers
(POSTDIV), and system clock dividers (SYSCLKn). Modification of the POSTDIV and SYSCLK values
does not require relocking the PLL and provides lower latency to switch between operating points, but at
the expense of the frequencies being limited by the integer divide values (only the divide values are
altered the PLL multiplier is left unmodified). Non integer divide frequency values can be achieved by
changing both the multiplier and the divide values, but when the PLL multiplier is changed the PLL must
relock, incurring additional latency to change between operating points. Detailed information on modifying
the PLL Controller settings can be found in
Reference Guide.
Voltage scaling is enabled from outside the device by controlling an external voltage regulator. The
processor may communicate with the regulator using GPIOs, I2C or some other interface. When switching
between voltage-frequency operating points, the voltage must always support the desired frequency.
When moving from a high-performance operating point to a lower performance operating point, the
frequency should be lowered first followed by the voltage. When moving from a low-performance operating
point to a higher performance operating point, the voltage should be raised first followed by the frequency.
Voltage operating points refer to the CVdd voltage at that point. Other static supplies must be maintained
at their nominal voltages at all operating points.
Copyright © 2010–2014, Texas Instruments Incorporated
(1)
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SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
Default
MIN
Value
N/A
1000
Max PLL Lock Time =
N/A
N/A
/1
/1
30 (if internal oscillator is used)
12
50 (if external clock source is used)
x20
x4
N/A
300
/1
/1
- AM1808/AM1810 ARM Microprocessor System
Peripheral Information and Electrical Specifications
AM1808
AM1808
MAX
N/A
2000 N
m
OSCIN
where N = Pre-Divider Ratio
cycles
M = PLL Multiplier
/32
x32
600
/32
UNIT
ns
MHz
MHz
79
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