Texas Instruments AM1808 User Manual page 134

AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
6.15.1 McASP Peripheral Registers Description(s)
Registers for the McASP are summarized in
peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can
also be accessed through the DMA port, as listed in
Registers for the McASP Audio FIFO (AFIFO) are summarized in
FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control
registers are accessed through the peripheral configuration port.
Table 6-49. McASP Registers Accessed Through Peripheral Configuration Port
BYTE ADDRESS ACRONYM
0x01D0 0000
0x01D0 0010
0x01D0 0014
0x01D0 0018
0x01D0 001C
0x01D0 001C
0x01D0 0020
0x01D0 0044
0x01D0 0048
0x01D0 004C
0x01D0 0050
0x01D0 0060
RGBLCTL
0x01D0 0064
0x01D0 0068
0x01D0 006C AFSRCTL
0x01D0 0070 ACLKRCTL
0x01D0 0074 AHCLKRCTL
0x01D0 0078
0x01D0 007C RINTCTL
0x01D0 0080
0x01D0 0084
0x01D0 0088 RCLKCHK
0x01D0 008C REVTCTL
0x01D0 00A0
XGBLCTL
0x01D0 00A4
0x01D0 00A8
0x01D0 00AC AFSXCTL
0x01D0 00B0 ACLKXCTL
0x01D0 00B4 AHCLKXCTL
0x01D0 00B8
0x01D0 00BC XINTCTL
0x01D0 00C0
0x01D0 00C4
0x01D0 00C8 XCLKCHK
0x01D0 00CC XEVTCTL
0x01D0 0100 DITCSRA0
0x01D0 0104 DITCSRA1
0x01D0 0108 DITCSRA2
134 Peripheral Information and Electrical Specifications
REV Revision identification register
PFUNC Pin function register
PDIR Pin direction register
PDOUT Pin data output register
PDIN Read returns: Pin data input register
PDSET Writes affect: Pin data set register (alternate write address: PDOUT)
PDCLR Pin data clear register (alternate write address: PDOUT)
GBLCTL Global control register
AMUTE Audio mute control register
DLBCTL Digital loopback control register
DITCTL DIT mode control register
Receiver global control register: Alias of GBLCTL, only receive bits are affected - allows
receiver to be reset independently from transmitter
RMASK Receive format unit bit mask register
RFMT Receive bit stream format register
Receive frame sync control register
Receive clock control register
Receive high-frequency clock control register
RTDM Receive TDM time slot 0-31 register
Receiver interrupt control register
RSTAT Receiver status register
RSLOT Current receive TDM time slot register
Receive clock check control register
Receiver DMA event control register
Transmitter global control register. Alias of GBLCTL, only transmit bits are affected - allows
transmitter to be reset independently from receiver
XMASK Transmit format unit bit mask register
XFMT Transmit bit stream format register
Transmit frame sync control register
Transmit clock control register
Transmit high-frequency clock control register
XTDM Transmit TDM time slot 0-31 register
Transmitter interrupt control register
XSTAT Transmitter status register
XSLOT Current transmit TDM time slot register
Transmit clock check control register
Transmitter DMA event control register
Left (even TDM time slot) channel status register (DIT mode) 0
Left (even TDM time slot) channel status register (DIT mode) 1
Left (even TDM time slot) channel status register (DIT mode) 2
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Table 6-49. The registers are accessed through the
Table 6-50
Table 6-51. Note that the AFIFO Write
REGISTER DESCRIPTION
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