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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
NO.
Max delay for slave to deassert
SPI1_ENA after final SPI1_CLK
18
t
d(SPC_ENA)M
edge to ensure master does not
begin the next transfer.
Delay from final SPI1_CLK edge to
20
t
d(SPC_SCS)M
master deasserting SPI1_SCS
Max delay for slave SPI to drive SPI1_ENA valid after master
21
t
asserts SPI1_SCS to delay the
d(SCSL_ENAL)M
master from beginning the next transfer,
Delay from SPI1_SCS active to first
22
t
(7) (8) (9)
d(SCS_SPC)M
SPI1_CLK
(1) These parameters are in addition to the general timings for SPI master modes
(2) P = SYSCLK2 period; M = t
(SPI master bit clock period)
c(SPC)M
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.
(8) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
164
Peripheral Information and Electrical Specifications
Table 6-80. Additional
PARAMETER
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
(4)
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK falling
(5) (6)
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
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(1)
SPI1 Master Timings, 5-Pin Option
1.3V, 1.2V
MIN
MAX
0.5M+P+5
P+5
0.5M+P+5
P+5
0.5M+P-1
P-1
0.5M+P-1
P-1
C2TDELAY+P
2P-1
0.5M+2P-1
0.5M+2P-5
2P-1
0.5M+2P-1
0.5M+2P-5
(Table
6-77).
AM1808
(2) (3)
1.1V
1.0V
MIN
MAX
MIN
0.5M+P+5
P+5
0.5M+P+5
P+5
0.5M+P-5
0.5M+P-6
P-5
P-6
0.5M+P-5
0.5M+P-6
P-5
P-6
C2TDELAY+P
2P-5
2P-6
0.5M+2P-6
2P-5
2P-6
0.5M+2P-6
Copyright © 2010–2014, Texas Instruments Incorporated
www.ti.com
UNIT
MAX
0.5M+P+6
P+6
ns
0.5M+P+6
P+6
ns
C2TDELAY+P
ns
ns
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