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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
NO.
Delay from slave assertion of SPI0_ENA
17
t
d(ENA_SPC)M
active to first SPI0_CLK from master.
Max delay for slave to deassert SPI0_ENA
18
t
after final SPI0_CLK edge to ensure
d(SPC_ENA)M
master does not begin the next transfer.
(1) These parameters are in addition to the general timings for SPI master modes
(2) P = SYSCLK2 period; M = t
(SPI master bit clock period)
c(SPC)M
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI0_EN A deassertion.
NO.
Delay from SPI0_SCS active to first
19
t
d(SCS_SPC)M
(4) (5)
SPI0_CLK
(1) These parameters are in addition to the general timings for SPI master modes
(2) P = SYSCLK2 period; M = t
(SPI master bit clock period)
c(SPC)M
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
156
Peripheral Information and Electrical Specifications
Table 6-70. Additional SPI0 Master Timings, 4-Pin Enable Option
PARAMETER
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Polarity = 0, Phase = 1,
to SPI0_CLK rising
(4)
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
(5)
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
(Table
Table 6-71. Additional SPI0 Master Timings, 4-Pin Chip Select Option
PARAMETER
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
(Table
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1.3V, 1.2V
MIN
MAX
MIN
3P+5
0.5M+3P+5
3P+5
0.5M+3P+5
0.5M+P+5
P+5
0.5M+P+5
P+5
6-68).
1.3V, 1.2V
MIN
MAX
2P-1
0.5M+2P-1
0.5M+2P-2
2P-1
0.5M+2P-1
0.5M+2P-2
6-68).
AM1808
(1) (2) (3)
1.1V
1.0V
MAX
MIN
MAX
3P+5
3P+6
0.5M+3P+5
0.5M+3P+6
3P+5
3P+6
0.5M+3P+5
0.5M+3P+6
0.5M+P+5
0.5M+P+6
P+5
P+6
0.5M+P+5
0.5M+P+6
P+5
P+6
(1) (2) (3)
1.1V
1.0V
MIN
MAX
MIN
2P-2
2P-3
0.5M+2P-3
2P-2
2P-3
0.5M+2P-3
Copyright © 2010–2014, Texas Instruments Incorporated
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UNIT
ns
ns
UNIT
MAX
ns
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