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Table 6-71. Additional SPI0 Master Timings, 4-Pin Chip Select Option
NO.
Delay from final SPI0_CLK edge to master
20
t
d(SPC_SCS)M
deasserting SPI0_SCS
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
NO.
Max delay for slave to deassert
SPI0_ENA after final SPI0_CLK
18
t
d(SPC_ENA)M
edge to ensure master does not
begin the next transfer.
Delay from final SPI0_CLK edge to from SPI0_CLK falling
20
t
master deasserting SPI0_SCS
d(SPC_SCS)M
(6)
Max delay for slave SPI to drive SPI0_ENA valid after master
21
t
asserts SPI0_SCS to delay the master from beginning the
d(SCSL_ENAL)M
next transfer,
(1) These parameters are in addition to the general timings for SPI master modes
(2) P = SYSCLK2 period; M = t
(SPI master bit clock period)
c(SPC)M
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
Copyright © 2010–2014, Texas Instruments Incorporated
PARAMETER
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK falling
(6) (7)
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Table 6-72. Additional SPI0 Master Timings, 5-Pin Option
PARAMETER
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
(4)
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
(5)
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
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1.3V, 1.2V
MIN
MAX
0.5M+P-1
P-1
0.5M+P-1
P-1
1.3V, 1.2V
MIN
MAX
0.5M+P+5
P+5
0.5M+P+5
P+5
0.5M+P-2
0.5M+P-2
P-2
0.5M+P-2
0.5M+P-2
P-2
C2TDELAY+P
(Table
6-69).
AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
(1)(2)(3)
(continued)
1.1V
MIN
MAX
MIN
0.5M+P-2
0.5M+P-3
P-2
P-3
0.5M+P-2
0.5M+P-3
P-2
P-3
(1) (2) (3)
1.1V
1.0V
MIN
MAX
MIN
0.5M+P+5
P+5
0.5M+P+5
P+5
0.5M+P-3
P-2
P-3
0.5M+P-3
P-2
P-3
C2TDELAY+P
Peripheral Information and Electrical Specifications
AM1808
1.0V
UNIT
MAX
ns
UNIT
MAX
0.5M+P+6
P+6
ns
0.5M+P+6
P+6
ns
C2TDELAY+P
ns
157
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