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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
NO.
1
t
Cycle time, AHCLKR/X
c(AHCLKRX)
2
t
Pulse duration, AHCLKR/X high or low
w(AHCLKRX)
3
t
Cycle time, ACLKR/X
c(ACLKRX)
4
t
Pulse duration, ACLKR/W high or low
w(ACLKRX)
Setup time,
5
t
su(AFSRX-ACLKRX)
AFSR/X input to ACLKR/X
Hold time,
6
t
h(ACLKRX-AFSRX)
AFSR/X input after ACLKR/X
Setup time,
7
t
su(AXR-ACLKRX)
AXR0[n] input to ACLKR/X
Hold time,
8
t
h(ACLKRX-AXR)
AXR0[n] input after ACLKR/X
(1) ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) This timing is limited by the timing shown or 2P, whichever is greater.
(4) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
(5) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
138
Peripheral Information and Electrical Specifications
Table 6-53. Timing Requirements for McASP0 (1.0V)
(4)
(4)
(4) (5)
(4) (5)
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(1) (2)
AHCLKR/X ext
AHCLKR/X ext
AHCLKR/X int
AHCLKR/X ext input
AHCLKR/X ext output
AHCLKR/X int
AHCLKR/X ext input
AHCLKR/X ext output
AHCLKR/X int
AHCLKR/X ext
AHCLKR/X int
AHCLKR/X ext input
AHCLKR/X ext output
Copyright © 2010–2014, Texas Instruments Incorporated
AM1808
www.ti.com
1.0V
UNIT
MIN
MAX
35
ns
17.5
ns
(3)
35
ns
17.5
ns
16
ns
5.5
ns
5.5
ns
-2
ns
1
ns
1
ns
16
ns
5.5
ns
-2
ns
5
ns
5
ns
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