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Table 6-118. Video Port Interface (VPIF) Registers (continued)
BYTE ADDRESS
0x01E1 714C
0x01E1 7150
0x01E1 7154
0x01E1 7158
0x01E1 715C
0x01E1 7160
0x01E1 7164
0x01E1 7168
0x01E1 716C
0x01E1 7170
0x01E1 7174
0x01E1 7178
0x01E1 717C
0x01E1 7180
0x01E1 7184
0x01E1 7188
0x01E1 718C
0x01E1 7190
0x01E1 7194
0x01E1 7198
0x01E1 719C
0x01E1 71A0 - 0x01E1 71FF
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ACRONYM
CH3_BC_STRTADR
Channel 3 Field 1 chroma buffer start address
CH3_THA_STRTADR
Channel 3 Field 0 horizontal ancillary data buffer start address
CH3_BHA_STRTADR
Channel 3 Field 1 horizontal ancillary data buffer start address
CH3_TVA_STRTADR
Channel 3 Field 0 vertical ancillary data buffer start address
CH3_BVA_STRTADR
Channel 3 Field 1 vertical ancillary data buffer start address
CH3_SUBPIC_CFG
Channel 3 sub-picture configuration
CH3_IMG_ADD_OFST
Channel 3 image data address offset
CH3_HA_ADD_OFST
Channel 3 horizontal ancillary data address offset
CH3_HSIZE_CFG
Channel 3 horizontal data size configuration
CH3_VSIZE_CFG0
Channel 3 vertical data size configuration (0)
CH3_VSIZE_CFG1
Channel 3 vertical data size configuration (1)
CH3_VSIZE_CFG2
Channel 3 vertical data size configuration (2)
CH3_VSIZE
Channel 3 vertical image size
CH3_THA_STRTPOS
Channel 3 Top Field horizontal ancillary data insertion start position
CH3_THA_SIZE
Channel 3 Top Field horizontal ancillary data size
CH3_BHA_STRTPOS
Channel 3 Bottom Field horizontal ancillary data insertion start position
CH3_BHA_SIZE
Channel 3 Bottom Field horizontal ancillary data size
CH3_TVA_STRTPOS
Channel 3 Top Field vertical ancillary data insertion start position
CH3_TVA_SIZE
Channel 3 Top Field vertical ancillary data size
CH3_BVA_STRTPOS
Channel 3 Bottom Field vertical ancillary data insertion start position
CH3_BVA_SIZE
Channel 3 Bottom Field vertical ancillary data size
-
Reserved
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SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
REGISTER DESCRIPTION
Peripheral Information and Electrical Specifications
AM1808
AM1808
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