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6.26.1 uPP Register Descriptions
BYTE ADDRESS
0x01E1 6000
0x01E1 6004
0x01E1 6008
0x01E1 6010
0x01E1 6014
0x01E1 6018
0x01E1 601C
0x01E1 6020
0x01E1 6024
0x01E1 6028
0x01E1 602C
0x01E1 6030
0x01E1 6040
0x01E1 6044
0x01E1 6048
0x01E1 6050
0x01E1 6054
0x01E1 6058
0x01E1 6060
0x01E1 6064
0x01E1 6068
0x01E1 6070
0x01E1 6074
0x01E1 6078
Copyright © 2010–2014, Texas Instruments Incorporated
Table 6-115. Universal Parallel Port (uPP) Registers
ACRONYM
UPPID
uPP Peripheral Identification Register
UPPCR
uPP Peripheral Control Register
UPDLB
uPP Digital Loopback Register
UPCTL
uPP Channel Control Register
UPICR
uPP Interface Configuration Register
UPIVR
uPP Interface Idle Value Register
UPTCR
uPP Threshold Configuration Register
UPISR
uPP Interrupt Raw Status Register
UPIER
uPP Interrupt Enabled Status Register
UPIES
uPP Interrupt Enable Set Register
UPIEC
uPP Interrupt Enable Clear Register
UPEOI
uPP End-of-Interrupt Register
UPID0
uPP DMA Channel I Descriptor 0 Register
UPID1
uPP DMA Channel I Descriptor 1 Register
UPID2
uPP DMA Channel I Descriptor 2 Register
UPIS0
uPP DMA Channel I Status 0 Register
UPIS1
uPP DMA Channel I Status 1 Register
UPIS2
uPP DMA Channel I Status 2 Register
UPQD0
uPP DMA Channel Q Descriptor 0 Register
UPQD1
uPP DMA Channel Q Descriptor 1 Register
UPQD2
uPP DMA Channel Q Descriptor 2 Register
UPQS0
uPP DMA Channel Q Status 0 Register
UPQS1
uPP DMA Channel Q Status 1 Register
UPQS2
uPP DMA Channel Q Status 2 Register
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SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
REGISTER DESCRIPTION
Peripheral Information and Electrical Specifications
AM1808
AM1808
219
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