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Table 6-54. Switching Characteristics for McASP0 (1.3V, 1.2V, 1.1V)
NO.
9
t
Cycle time, AHCLKR/X
c(AHCLKRX)
10
t
Pulse duration, AHCLKR/X high or low
w(AHCLKRX)
11
t
Cycle time, ACLKR/X
c(ACLKRX)
12
t
Pulse duration, ACLKR/X high or low ACLKR/X int
w(ACLKRX)
Delay time, ACLKR/X transmit edge
13
t
d(ACLKRX-AFSRX)
to AFSX/R output valid
Delay time, ACLKX transmit edge to
14
t
d(ACLKX-AXRV)
AXR output valid
Disable time, ACLKR/X transmit
15
t
edge to AXR high impedance
dis(ACLKX-AXRHZ)
following last data bit
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(3) P = SYSCLK2 period
(4) This timing is limited by the timing shown or 2P, whichever is greater.
(5) A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(6) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
NO.
9
t
Cycle time, AHCLKR/X
c(AHCLKRX)
10
t
Pulse duration, AHCLKR/X high or low
w(AHCLKRX)
11
t
Cycle time, ACLKR/X
c(ACLKRX)
12
t
Pulse duration, ACLKR/X high or low
w(ACLKRX)
Delay time, ACLKR/X transmit edge to AFSX/R output
13
t
d(ACLKRX-AFSRX)
valid
14
t
Delay time, ACLKX transmit edge to AXR output valid
d(ACLKX-AXRV)
Disable time, ACLKR/X transmit edge to AXR high
15
t
dis(ACLKX-AXRHZ)
impedance following last data bit
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(3) P = SYSCLK2 period
(4) This timing is limited by the timing shown or 2P, whichever is greater.
(5) A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(6) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
Copyright © 2010–2014, Texas Instruments Incorporated
PARAMETER
(6)
Table 6-55. Switching Characteristics for McASP0 (1.0V)
PARAMETER
(6)
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SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
1.3V, 1.2V
MIN
25
AH – 2.5
(3) (4)
ACLKR/X int
25
A – 2.5
ACLKR/X int
-1
ACLKR/X ext input
2
ACLKR/X ext output
2
ACLKR/X int
-1
ACLKR/X ext input
2
ACLKR/X ext output
2
ACLKR/X int
0
ACLKR/X ext
2
ACLKR/X int
ACLKR/X int
ACLKR/X int
ACLKR/X ext input
ACLKR/X ext output
ACLKR/X int
ACLKR/X ext input
ACLKR/X ext output
ACLKR/X int
ACLKR/X ext
Peripheral Information and Electrical Specifications
AM1808
(1)
1.1V
MAX
MIN
MAX
28
(2)
(2)
AH – 2.5
(3) (4)
28
(5)
(5)
A – 2.5
6
-1
8
13.5
2
14.5
13.5
2
14.5
6
-1
8
13.5
2
15
13.5
2
15
6
0
8
13.5
2
15
(1)
1.0V
MIN
MAX
35
(2)
AH – 2.5
(3) (4)
35
(5)
A – 2.5
-0.5
10
2
19
2
19
-0.5
10
2
19
2
19
0
10
2
19
AM1808
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
139
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