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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
Table 6-3. OSCIN Timing Requirements for an Externally Driven Clock
f
OSCIN frequency range
OSCIN
t
Cycle time, external clock driven on OSCIN
c(OSCIN)
t
Pulse width high, external clock on OSCIN
w(OSCINH)
t
Pulse width low, external clock on OSCIN
w(OSCINL)
t
Transition time, OSCIN
t(OSCIN)
t
Period jitter, OSCIN
j(OSCIN)
(1) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
6.6
Clock PLLs
The device has two PLL controllers that provide clocks to different parts of the system. PLL0 provides
clocks (though various dividers) to most of the components of the device. PLL1 provides clocks to the
mDDR/DDR2 Controller and provides an alternate clock source for the ASYNC3 clock domain. This allows
the peripherals on the ASYNC3 clock domain to be immune to frequency scaling operation on PLL0.
The PLL controller provides the following:
•
Glitch-Free Transitions (on changing clock settings)
•
Domain Clocks Alignment
•
Clock Gating
•
PLL power down
The various clock outputs given by the controller are as follows:
•
Domain Clocks: SYSCLK [1:n]
•
Auxiliary Clock from reference clock source: AUXCLK
Various dividers that can be used are as follows:
•
Post-PLL Divider: POSTDIV
•
SYSCLK Divider: D1, ¼, Dn
Various other controls supported are as follows:
•
PLL Multiplier Control: PLLM
•
Software programmable PLL Bypass: PLLEN
76
Peripheral Information and Electrical Specifications
OSCIN
OSCOUT
NC
OSCV
SS
Figure 6-7. External 1.2V Clock Source
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Product Folder Links:
Clock
Input
to PLL
MIN
12
20
0.4 t
c(OSCIN)
0.4 t
c(OSCIN)
Copyright © 2010–2014, Texas Instruments Incorporated
AM1808
www.ti.com
MAX
UNIT
50
MHz
ns
ns
ns
(1)
0.25P or 10
ns
0.02P
ns
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