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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
Table 6-63. Switching Characteristics for McBSP1 [1.3V, 1.2V, 1.1V]
NO.
Delay time, CLKS high to CLKR/X high for internal
1
t
d(CKSH-CKRXH)
CLKR/X generated from CLKS input
2
t
Cycle time, CLKR/X
c(CKRX)
Pulse duration, CLKR/X high or
3
t
w(CKRX)
CLKR/X low
Delay time, CLKR high to internal
4
t
d(CKRH-FRV)
FSR valid
Delay time, CLKX high to internal
9
t
d(CKXH-FXV)
FSX valid
Disable time, DX high impedance
12
t
following last data bit from CLKX
dis(CKXH-DXHZ)
high
13
t
Delay time, CLKX high to DX valid
d(CKXH-DXV)
Delay time, FSX high to DX valid
14
t
ONLY applies when in data
d(FXH-DXV)
delay 0 (XDATDLY = 00b) mode
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
(4) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(5) Use whichever value is greater.
(6) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
(7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(9) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
148
Peripheral Information and Electrical Specifications
(see
PARAMETER
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
FSX ext
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Figure
6-32)
1.3V, 1.2V
MIN
MAX
0.5
16.5
(3) (4) (5)
2P or 20
(6)
(6)
C - 2
C + 2
-4
6.5
1
16.5
-4
6.5
1
16.5
-4
6.5
-2
16.5
(7)
-4 + D1
6.5 + D2
(7)
1 + D1
16.5 + D2
(8)
(8)
-4
6.5
(8)
(8)
-2
16.5
Copyright © 2010–2014, Texas Instruments Incorporated
AM1808
(1) (2)
1.1V
MIN
MAX
1.5
18
(3) (4) (5)
2P or 25
(6)
(6)
C - 2
C + 2
-4
13
1
18
-4
13
1
18
-4
13
-2
18
(7)
(7)
-4 + D1
13 + D2
(7)
(7)
1 + D1
18 + D2
(8)
(8)
-4
13
(8)
(9)
-2
18
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UNIT
ns
ns
ns
ns
ns
ns
(7)
ns
(7)
ns
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