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AVDD to the ground plane. Connect a 1.0-µF capacitor from DVDD to the ground plane. Connect a 1.0-µF capacitor from BYPASS to the ground plane. For details on power supply recommendations, see the ADS125H02 ±20-V Input, 2-Channel, 40- kSPS, 24-Bit, Delta-Sigma ADC With PGA and Voltage Reference Data Sheet.
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HV_AVSS 6. GPIO configuration: The ADS125H02 device provides four GPIO pins (GPIO0–GPIO4), two GPIOs are available on dedicated pins and two GPIOs are multiplexed functions with an external reference (REFP1 and REFN1). The GPIO input and output levels are referred to AVDD and AGND, so in this case the logic output levels are set to 5.0V.
Digital low-pass filters are essential to the functionality of a delta-sigma ADC, which relies on oversampling and noise shaping to push quantization noise out of band. There are a variety of options for digital filters available in the ADS125H02 device. When choosing a digital filter, consider the following tradeoffs: •...
The dedicated DRDY pin indicates the availability of new conversion data. Pseudocode is shown without the use of the STATUS byte and CRC data verification. Download the ADS125H02 Example C Code from the ADS125H02 product folder or access it directly with the following...
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TI's comprehensive circuit library. Power Supply Reference Designs The ADS125H02 device requires three analog power supplies (high-voltage supplies HV_AVDD and HV_AVSS, and low-voltage analog supply AVDD) and a digital power supply (DVDD). This circuit assumes a bipolar supply (±15.0 V) for HV_AVDD and HV_AVSS, and a 5.0-V supply. The following table shows there are specifications for three reference designs that could be used to provide the power supplies from a 24.0 V nominal input voltage.
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