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Table 6-69. General Timing Requirements for SPI0 Slave Modes
NO.
9
t
Cycle Time, SPI0_CLK, All Slave Modes
c(SPC)S
10
t
Pulse Width High, SPI0_CLK, All Slave Modes
w(SPCH)S
11
t
Pulse Width Low, SPI0_CLK, All Slave Modes
w(SPCL)S
Setup time, transmit data
written to SPI before initial
12
t
su(SOMI_SPC)S
clock edge from
(3) (4)
master.
Delay, subsequent bits valid from SPI0_CLK falling
13
t
on SPI0_SOMI after
d(SPC_SOMI)S
transmit edge of SPI0_CLK
Output hold time,
14
t
SPI0_SOMI valid after
oh(SPC_SOMI)S
receive edge of SPI0_CLK
Input Setup Time,
15
t
SPI0_SIMO valid before
su(SIMO_SPC)S
receive edge of SPI0_CLK
Input Hold Time,
16
t
SPI0_SIMO valid after
ih(SPC_SIMO)S
receive edge of SPI0_CLK
(1) P = SYSCLK2 period; S = t
(2) This timing is limited by the timing shown or 3P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
(4) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
Copyright © 2010–2014, Texas Instruments Incorporated
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK rising
Polarity = 0, Phase = 1,
Polarity = 1, Phase = 0,
from SPI0_CLK falling
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
Polarity = 0, Phase = 0,
to SPI0_CLK falling
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK rising
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
(SPI slave bit clock period)
c(SPC)S
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SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
1.3V, 1.2V
1.1V
MIN
MAX
MIN
(2)
(2)
40
50
18
22
18
22
2P
2P
2P
2P
2P
2P
2P
2P
17
17
17
17
0.5S-6
0.5S-16
0.5S-6
0.5S-16
0.5S-6
0.5S-16
0.5S-6
0.5S-16
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
4
4
4
4
4
4
4
4
Peripheral Information and Electrical Specifications
AM1808
AM1808
(1)
1.0V
UNIT
MAX
MIN
MAX
(2)
60
ns
27
ns
27
ns
2P
2P
ns
2P
2P
20
27
20
27
ns
20
27
20
27
0.5S-20
0.5S-20
ns
0.5S-20
0.5S-20
1.5
1.5
ns
1.5
1.5
5
5
ns
5
5
155
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