Texas Instruments AM1808 User Manual page 80

AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
The maximum voltage slew rate for CVdd supply changes is 1 mV/us.
For additional information on power management solutions from TI for this processor, follow the Power
Management link in the Product Folder on
The processor supports multiple clock domains some of which have clock ratio requirements to each
other. PLL0_SYSCLK2:PLL0_SYSCLK4:PLL0_SYSCLK6 are synchronous to each other and the
SYSCLKn dividers must always be configured such that the ratio between these domains is 2:4:1. The
ASYNC and ASYNC3 clock domains are asynchronous to the other clock domains and have no specific
ratio requirement.
The table below summarizes the maximum internal clock frequencies at each of the voltage operating
points.
Table 6-5. Maximum Internal Clock Frequencies at Each Voltage Operating Point
CLOCK SOURCE
PLL0_SYSCLK1 Not used on this processor
SYSCLK2 clock domain peripherals and optional clock source
PLL0_SYSCLK2
for ASYNC3 clock domain peripherals
PLL0_SYSCLK3 Optional clock for ASYNC1 clock domain
PLL0_SYSCLK4 SYSCLK4 domain peripherals
PLL0_SYSCLK5 Not used on this processor
PLL0_SYSCLK6 ARM subsystem
PLL0_SYSCLK7 Optional 50 MHz clock source for EMAC RMII interface
DDR2/mDDR Interface clock source (memory interface clock
PLL1_SYSCLK1
is one-half of the value shown)
PLL1_SYSCLK2 Optional clock source for ASYNC3 clock domain peripherals
PLL1_SYSCLK3 Alternate clock source input to PLL Controller 0
McASP AUXCLK Bypass clock source for the McASP
PLL0_AUXCLK Bypass clock source for the USB0 and USB1
ASYNC1 ASYNC1 Clock Domain (EMIFA)
ASYNC2 ASYNC2 Clock Domain (multiple peripherals)
Some interfaces have specific limitations on supported modes/speeds at each operating point. See the
corresponding peripheral sections of this document for more information.
TI provides software components (called the Power Manager) to perform DVFS and abstract the task from
the user. The Power Manager controls changing operating points (both frequency and voltage) and
handles the related tasks involved such as informing/controlling peripherals to provide graceful transitions
between operating points.
80 Peripheral Information and Electrical Specifications
www.ti.com
CLOCK DOMAIN
Async Mode
SDRAM Mode
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Product Folder Links:
for this processor.
1.3V NOM 1.2V NOM
- -
228 MHz 187.5 MHz
114 MHz 93.75 MHz
- -
456 MHz 375 MHz
50 MHz 50 MHz
312 MHz 312 MHz
152 MHz 150 MHz
75 MHz 75 MHz
50 MHz 50 MHz
48 MHz 48 MHz
148 MHz 148 MHz
100 MHz 100 MHz
50 MHz 50 MHz
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AM1808
www.ti.com
1.1V NOM 1.0V NOM
- -
100 MHz 50 MHz
50 MHz 25 MHz
- -
200 MHz 100 MHz
- -
300 MHz 266 MHz
100 MHz 75 MHz
75 MHz 75 MHz
50 MHz 50 MHz
48 MHz 48 MHz
75 MHz 50 MHz
66.6 MHz 50 MHz
50 MHz 50 MHz