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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
6.20.2 USB0 [USB2.0] Electrical Data/Timing
The USB PHY PLL can support input clock of the following frequencies: 12.0 MHz, 13.0 MHz, 19.2 MHz,
20.0 MHz, 24.0 MHz, 26.0 MHz, 38.4 MHz, 40.0 MHz or 48.0 MHz. USB_REFCLKIN jitter tolerance is 50
ppm maximum.
Table 6-91. Switching Characteristics Over Recommended Operating Conditions for USB0 [USB2.0] (see
NO.
1
t
Rise time, USB_DP and USB_DM signals
r(D)
2
t
Fall time, USB_DP and USB_DM signals
f(D)
3
t
Rise/Fall time, matching
rfM
4
V
Output signal cross-over voltage
CRS
5
t
Source (Host) Driver jitter, next transition
jr(source)NT
t
Function Driver jitter, next transition
jr(FUNC)NT
6
t
Source (Host) Driver jitter, paired transition
jr(source)PT
t
Function Driver jitter, paired transition
jr(FUNC)PT
7
t
Pulse duration, EOP transmitter
w(EOPT)
8
t
Pulse duration, EOP receiver
w(EOPR)
9
t
Data Rate
(DRATE)
10
Z
Driver Output Resistance
DRV
11
Z
Receiver Input Impedance
INP
(1) Low Speed: C
= 200 pF, Full Speed: C
L
(2) t
= (t
/t
) x 100. [Excluding the first transaction from the Idle state.]
RFM
r
f
(3) For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7. Electrical.
(4) t
= t
- t
jr
px(1)
px(0)
USB_DM
V
CRS
USB_DP
Figure 6-44. USB2.0 Integrated Transceiver Interface Timing
184
Peripheral Information and Electrical Specifications
Figure
PARAMETER
(1)
(1)
(2)
(1)
(4)
= 50 pF, High Speed: C
L
10% V
OL
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6-44)
1.3V, 1.2V, 1.1V, 1.0V
LOW SPEED
1.5 Mbps
MIN
MAX
75
300
75
300
80
120
1.3
2
2
25
1
10
1250
1500
670
1.5
–
–
100k
= 50 pF
L
t
t
per −
jr
90% V
OH
t
f
t
r
Copyright © 2010–2014, Texas Instruments Incorporated
AM1808
www.ti.com
FULL SPEED
HIGH SPEED
12 Mbps
480 Mbps
MIN
MAX
MIN
MAX
4
20
0.5
4
20
0.5
90
111
–
1.3
2
–
2
2
1
1
160
175
–
82
–
12
40.5
49.5
40.5
49.5
100k
-
UNIT
ns
ns
–
%
–
V
(3)
ns
(3)
ns
(3)
ns
(3)
ns
–
ns
ns
480 Mb/s
Ω
-
Ω
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