Texas Instruments AM1808 User Manual page 99

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SDRAM
Memory Number of
Data Bus Memories
Width (bits)
1
1
1
1
1
16 1
1
1
1
1
1
1
2
2
2
2
2
8 2
2
2
2
2
2
2
(1) The shaded cells indicate configurations that are possible on the EMIFA interface but as of this writing SDRAM memories capable of
supporting these densities are not available in the market.
6.10.3 EMIFA SDRAM Loading Limitations
EMIFA supports SDRAM up to 100 MHz with up to two SDRAM or asynchronous memory loads.
Additional loads will limit the SDRAM operation to lower speeds and the maximum speed should be
confirmed by board simulation using IBIS models.
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Table 6-17. EMIFA Supported SDRAM Configurations
EMIFA Data
Bus Size Rows
(bits)
16 16
16 16
16 16
16 16
16 16
16 16
16 16
16 16
16 16
16 16
16 16
16 15
16 16
16 16
16 16
16 16
16 16
16 16
16 16
16 16
16 16
16 16
16 16
16 15
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Columns Banks
8 1
8 2
8 4
9 1
9 2
9 4
10 1
10 2
10 4
11 1
11 2
11 4
8 1
8 2
8 4
9 1
9 2
9 4
10 1
10 2
10 4
11 1
11 2
11 4
Peripheral Information and Electrical Specifications
AM1808
(1)
Total Total
Memory Memory
(Mbits) (Mbytes)
256 32
512 64
1024 128
512 64
1024 128
2048 256
1024 128
2048 256
4096 512
2048 256
4096 512
4096 512
256 32
512 64
1024 128
512 64
1024 128
2048 256
1024 128
2048 256
4096 512
2048 256
4096 512
4096 512
AM1808
Memory
Density
(Mbits)
256
512
1024
512
1024
2048
1024
2048
4096
2048
4096
4096
128
256
512
256
512
1024
512
1024
2048
1024
2048
2048
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