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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
Figure 6-22
shows the topology and routing for the DQS and D net class; the routes are point to point.
Skew matching across bytes is not needed nor recommended.
NO.
PARAMETER
1
Center to center DQS to other DDR2/mDDR trace spacing
2
DQS/D nominal trace length
3
D to DQS Skew Length Mismatch
4
D to D Skew Length Mismatch
5
Center to center D to other DDR2/mDDR trace spacing
6
Center to Center D to other D trace spacing
(1) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(2) w = PCB trace width as defined in
(3) Series terminator, if used, should be located closest to DDR.
(4) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte
1.
(5) D's from other DQS domains are considered other DDR2/mDDR trace.
(6) DQLM is the longest Manhattan distance of each of the DQS and D net class.
120
Peripheral Information and Electrical Specifications
T
E0
A1
T
E1
A1
Figure 6-22. DQS and D Routing and Topology
Table 6-35. DQS and D Routing Specification
(1)
(3) (4)
(4)
(4)
(1) (5)
(1) (6)
Table
6-27.
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Product Folder Links:
MIN
TYP
(2)
4w
DQLM-50
DQLM
(2)
4w
(2)
3w
Copyright © 2010–2014, Texas Instruments Incorporated
AM1808
www.ti.com
MAX
UNIT
DQLM+50
Mils
100
Mils
100
Mils
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