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6.4.3 Reset Electrical Data Timings
Table 6-1
assumes testing over the recommended operating conditions.
NO.
1
t
Pulse width, RESET/TRST low
w(RSTL)
2
t
Setup time, boot pins valid before RESET/TRST high
su(BPV-RSTH)
3
t
Hold time, boot pins valid after RESET/TRST high
h(RSTH-BPV)
t
RESET high to RESETOUT high; Warm reset
d(RSTH-
4
RESETOUTH)
RESET high to RESETOUT high; Power-on Reset
t
Delay time, RESET/TRST low to RESETOUT low
d(RSTL-
5
RESETOUTL)
(1) RESETOUT is multiplexed with other pin functions. See the Terminal Functions table,
(2) For power-on reset (POR), the reset timings in this table refer to RESET and TRST together. For warm reset, the reset timings in this
table refer to RESET only (TRST is held high).
(3) OSCIN cycles.
Power
Supplies
Ramping
OSCIN
RESET
TRST
RESETOUT
Boot Pins
Figure 6-4. Power-On Reset (RESET and TRST active) Timing
Copyright © 2010–2014, Texas Instruments Incorporated
Table 6-1. Reset Timing Requirements (
Clock Source Stable
1
3
2
Config
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SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
(1)
(2)
,
)
1.3V, 1.2V
MIN
MAX
MIN
100
100
20
20
20
20
4096
4096
6169
6169
14
Table 3-3
for details.
Power Supplies Stable
4
Peripheral Information and Electrical Specifications
AM1808
AM1808
1.1V
1.0V
UNIT
MAX
MIN
MAX
100
ns
20
ns
20
ns
4096
cycles
6169
ns
16
20
(3)
73
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