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Texas Instruments AM1808 Technical Reference Manual

Texas Instruments AM1808 Technical Reference Manual

Sitara arm microprocessor

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AM1808/AM1810

Sitara ARM Microprocessor

Technical Reference Manual

Literature Number: SPRUH82C

April 2013 – Revised September 2016

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Page 1 AM1808/AM1810 Sitara ARM Microprocessor Technical Reference Manual Literature Number: SPRUH82C April 2013 – Revised September 2016...
Page 2: Table Of Contents
Configuration Register (CONFIG) ............5.3.3 Interrupt Raw Status/Set Register (IRAWSTAT) ............5.3.4 Interrupt Enable Status/Clear Register (IENSTAT) ..............5.3.5 Interrupt Enable Set Register (IENSET) Contents SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 3 ............. 7.3.24 PLL Controller Command Register (PLLCMD) ..............7.3.25 PLL Controller Status Register (PLLSTAT) ............7.3.26 PLLC0 Clock Align Control Register (ALNCTL) SPRUH82C – April 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 4 Features ....................... Clock Management ..................9.5.1 Module Clock ON/OFF ................9.5.2 Module Clock Frequency Scaling ................. 9.5.3 PLL Bypass and Power Down Contents SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 5 10.5.21 Deep Sleep Register (DEEPSLEEP) ............10.5.22 Pullup/Pulldown Enable Register (PUPD_ENA) ............10.5.23 Pullup/Pulldown Select Register (PUPD_SEL) ..............10.5.24 RXACTIVE Control Register (RXACTIVE) SPRUH82C – April 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 6 11.4.35 Host Interrupt Nesting Level Register 1 (HINLR1) ............11.4.36 Host Interrupt Nesting Level Register 2 (HINLR2) ..............11.4.37 Host Interrupt Enable Register (HIER) Contents SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 7 14.2.17 Emulation Considerations ....................14.3 Supported Use Cases ........................14.4 Registers ................ 14.4.1 SDRAM Status Register (SDRSTAT) ..............14.4.2 SDRAM Configuration Register (SDCR) SPRUH82C – April 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 8 16.2.1 Overview ..............16.2.2 Proper Interrupt Initialization Procedure ................... 16.2.3 Time-Base (TB) Submodule ................16.2.4 Counter-Compare (CC) Submodule ................16.2.5 Action-Qualifier (AQ) Submodule Contents SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 9 17.2.18 Emulation Considerations ......................17.3 Transfer Examples ................... 17.3.1 Block Move Example ................17.3.2 Subframe Extraction Example ..................17.3.3 Data Sorting Example SPRUH82C – April 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 10 19.2.4 SDRAM Controller and Interface ..............19.2.5 Asynchronous Controller and Interface ....................19.2.6 Data Bus Parking ..............19.2.7 Reset and Initialization Considerations ....................19.2.8 Interrupt Support Contents SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 11 20.2.7 Using a GPIO Signal as an Input ..................20.2.8 Reset Considerations ...................... 20.2.9 Initialization ....................20.2.10 Interrupt Support ..................20.2.11 EDMA Event Support ..................20.2.12 Power Management SPRUH82C – April 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 12 22.1.1 Purpose of the Peripheral ......................22.1.2 Features ..................22.1.3 Functional Block Diagram ..............22.1.4 Industry Standard(s) Compliance Statement ........................ 22.2 Architecture ....................22.2.1 Bus Structure Contents SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 13 23.3.3 LCD Status Register (LCD_STAT) 1049 ..............23.3.4 LCD LIDD Control Register (LIDD_CTRL) 1052 ....23.3.5 LCD LIDD CSn Configuration Registers (LIDD_CS0_CONF and LIDD_CS1_CONF) 1054 SPRUH82C – April 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 14 24.1.29 Transmit Clock Control Register (ACLKXCTL) 1175 ........24.1.30 Transmit High-Frequency Clock Control Register (AHCLKXCTL) 1176 ............... 24.1.31 Transmit TDM Time Slot Register (XTDM) 1177 Contents SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 15 25.3.10 Pin Control Register (PCR) 1259 ........... 25.3.11 BFIFO Revision Identification Register (BFIFOREV) 1261 ............... 25.3.12 Write FIFO Control Register (WFIFOCTL) 1262 SPRUH82C – April 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 16 26.4.15 MMC Response Registers (MMCRSP0-MMCRSP7) 1312 ............26.4.16 MMC Data Response Register (MMCDRSP) 1314 ............26.4.17 MMC Command Index Register (MMCCIDX) 1314 Contents SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 17 28.1.5 Terminology Used in this Document 1346 ................28.1.6 Industry Standard(s) Compliance 1347 ......................28.2 Architecture 1348 ....................28.2.1 Clock Control 1348 SPRUH82C – April 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 18 28.4.33 Port DMA Control Register (P0DMACR) 1405 ..............28.4.34 Port PHY Control Register (P0PHYCR) 1407 ..............28.4.35 Port PHY Status Register (P0PHYSR) 1411 Contents SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 19 30.1.1 Purpose of the Peripheral 1468 ......................30.1.2 Features 1468 ....................30.1.3 Block Diagram 1469 ..............30.1.4 Industry Standard Compatibility Statement 1469 SPRUH82C – April 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 20 1522 ................31.3.7 Modem Control Register (MCR) 1524 .................. 31.3.8 Line Status Register (LSR) 1525 ................31.3.9 Modem Status Register (MSR) 1528 Contents SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 21 33.1.1 Purpose of the Peripheral 1581 ......................33.2 Architecture 1582 ....................33.2.1 Clock and Reset 1582 .............. 33.2.2 Open Host Controller Interface Functionality 1583 SPRUH82C – April 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 22 34.3.2 User Case 2: Example of How to Program the USB Endpoints in Peripheral Mode 1679 ......34.3.3 User Case 3: Example of How to Program the USB Endpoints in Host Mode 1680 Contents SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 23 34.4.50 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) 1731 ......... 34.4.51 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) 1732 SPRUH82C – April 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 24 Architecture 1763 ....................35.2.1 Clock Control 1763 .................... 35.2.2 Signal Descriptions 1763 ....................35.2.3 Memory Interface 1765 ....................35.2.4 Video Transmit 1767 Contents SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 25 35.3.39 Channel n Bottom Field Vertical Ancillary Position Register (C2BVANCPOS and ....................C3BVANCPOS) 1817 35.3.40 Channel n Bottom Field Vertical Ancillary Size Register (C2BVANCSIZE and C3BVANCSIZE) 1818 ........................Revision History 1819 SPRUH82C – April 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 26 List of Figures .............. 1-1. AM1808/AM1810 ARM Microprocessor Block Diagram ..................3-1. System Interconnect Block Diagram ....................... 5-1. MPU Block Diagram ......................5-2. Permission Fields ................... 5-3. Revision ID Register (REVID) ..................5-4. Configuration Register (CONFIG) ..............5-5. Interrupt Raw Status/Set Register (IRAWSTAT) ..............
Page 27 ..............10-8. Interrupt Raw Status/Set Register (IRAWSTAT) ..............10-9. Interrupt Enable Status/Clear Register (IENSTAT) ..................10-10. Interrupt Enable Register (IENSET) SPRUH82C – April 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 28 11-5. Global Enable Register (GER) ................11-6. Global Nesting Level Register (GNLR) ............... 11-7. System Interrupt Status Indexed Set Register (SISR) List of Figures SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 29 13-14. Format 4a: (Quick Arithmetic Test and Branch – Register Op2) ..........13-15. Format 4b: (Quick Arithmetic Test and Branch – Immediate Op2) SPRUH82C – April 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 30 14-29. Performance Counter Configuration Register (PCC) ..........14-30. Performance Counter Master Region Select Register (PCMRS) ................14-31. Performance Counter Time Register (PCT) List of Figures SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 31 16-11. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up on Synchronization Event ..................16-12. Counter-Compare Submodule ............... 16-13. Counter-Compare Submodule Signals and Registers ............16-14. Counter-Compare Event Waveforms in Up-Count Mode SPRUH82C – April 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 32 16-56. Half-H Bridge Waveforms for (Note: F PWM2 PWM1 ....... 16-57. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control List of Figures SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 33 17-9. Link-to-Self Transfer Example ................... 17-10. QDMA Channel to PaRAM Mapping ....................17-11. Shadow Region Registers ......................17-12. Interrupt Diagram SPRUH82C – April 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 34 17-58. Queue n Status Register (QSTATn) ............. 17-59. Queue Watermark Threshold A Register (QWMTHRA) ................17-60. EDMA3CC Status Register (CCSTAT) ...................... 17-61. Event Register (ER) List of Figures SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 35 17-108. Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn) ..................18-1. EMAC and MDIO Block Diagram ................18-2. Ethernet Configuration—MII Connections SPRUH82C – April 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 36 18-47. Transmit Interrupt Mask Set Register (TXINTMASKSET) ............. 18-48. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ............... 18-49. MAC Input Vector Register (MACINVECTOR) List of Figures SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 37 19-8. EMIFA to 8-bit/16-bit Memory Interface ..................19-9. Common Asynchronous Interface ..........19-10. Timing Waveform of an Asynchronous Read Cycle in Normal Mode SPRUH82C – April 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 38 ..............20-5. GPIO Banks 2 and 3 Direction Register (DIR23) ..............20-6. GPIO Banks 4 and 5 Direction Register (DIR45) List of Figures SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 39 20-53. GPIO Bank 8 Interrupt Status Register (INTSTAT8) ....................... 21-1. HPI Block Diagram ..............21-2. Example of Host-Processor Signal Connections SPRUH82C – April 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 40 22-17. I2C Clock High-Time Divider Register (ICCLKH) 1008 ..................22-18. I2C Data Count Register (ICCNT) 1009 .................. 22-19. I2C Data Receive Register (ICDRR) 1010 List of Figures SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 41 23-31. LCD Raster Timing Register 1 (RASTER_TIMING_1) 1066 ............23-32. Vertical Synchronization Pulse Width (VSW) - Active Mode 1067 ..................... 23-33. Vertical Front Porch (VFP) 1068 SPRUH82C – April 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 42 24-37. Pin Direction Register (PDIR) 1141 ................... 24-38. Pin Data Output Register (PDOUT) 1143 ..................24-39. Pin Data Input Register (PDIN) 1145 List of Figures SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 43 25-6. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1 1201 ......25-7. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3 1201 SPRUH82C – April 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 44 25-54. Write FIFO Status Register (WFIFOSTS) 1263 ................25-55. Read FIFO Control Register (RFIFOCTL) 1264 ................25-56. Read FIFO Status Register (RFIFOSTS) 1265 List of Figures SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 45 27-4. Second Register (SECOND) 1328 ..................... 27-5. Minute Register (MINUTE) 1328 ....................27-6. Hour Register (HOUR) 1329 ....................27-7. Days Register (DAY) 1330 SPRUH82C – April 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 46 1403 .............. 28-31. Port Serial ATA Active (SActive) Register (P0SACT) 1403 ..............28-32. Port Serial ATA Notification Register (POSNTF) 1404 List of Figures SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 47 1474 ................. 30-5. Dual 32-Bit Timers Chained Mode Example 1474 ............... 30-6. Dual 32-Bit Timers Unchained Mode Block Diagram 1476 SPRUH82C – April 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 48 31-24. Mode Definition Register (MDR) 1533 ..................32-1. uPP Functional Block Diagram 1536 ............... 32-2. Data Flow for Single-Channel Receive Mode 1536 List of Figures SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 49 33-8. HC HCAA Address Register (HCHCCA) 1593 ............33-9. HC Current Periodic Register (HCPERIODCURRENTED) 1593 .............. 33-10. HC Head Control Register (HCCONTROLHEADED) 1594 SPRUH82C – April 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 50 34-33. SRP Fix Time Register (SRPFIXTIME) 1699 ..................34-34. Teardown Register (TEARDOWN) 1699 ................34-35. USB Interrupt Source Register (INTSRCR) 1700 List of Figures SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 51 34-82. Receive Endpoint FIFO Size (RXFIFOSZ) 1734 ..............34-83. Transmit Endpoint FIFO Address (TXFIFOADDR) 1735 ..............34-84. Receive Endpoint FIFO Address (RXFIFOADDR) 1735 SPRUH82C – April 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 52 35-15. Clock Control on Video Input and Output with SDTV Encoding 1780 ..........35-16. Clock Control on Video Input and Output with HDTV Encoding 1782 List of Figures SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 53 35-56. Channel n Bottom Field Vertical Ancillary Position Register (CnBVANCPOS) 1817 ........35-57. Channel n Bottom Field Vertical Ancillary Size Register (CnBVANCSIZE) 1818 SPRUH82C – April 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 54 List of Tables ..................2-1. Exception Vector Table for ARM ................2-2. Different Address Types in ARM System ..........3-1. AM1808/AM1810 ARM Microprocessor System Interconnect Matrix ..................... 5-1. MPU Memory Regions ....................5-2. MPU Default Configuration ....................5-3. Device Master Settings ...................
Page 55 8-20. Power Domain 0 Configuration Register (PDCFG0) Field Descriptions ........... 8-21. Power Domain 1 Configuration Register (PDCFG1) Field Descriptions ............8-22. Module Status n Register (MDSTATn) Field Descriptions SPRUH82C – April 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 56 10-44. Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions ............ 10-45. Chip Configuration 0 Register (CFGCHIP0) Field Descriptions ............ 10-46. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions List of Tables SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 57 11-37. Host Interrupt Nesting Level Register 1 (HINLR1) Field Descriptions ..........11-38. Host Interrupt Nesting Level Register 2 (HINLR2) Field Descriptions SPRUH82C – April 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 58 13-43. INTCTER0 to INTCTER31 Register Field Descriptions ..................13-44. Instruction RAM Memory Region ................. 13-45. PRUSS Interrupt Controller (INTC) Registers ......................13-46. REVID Register List of Tables SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 59 ..................... 13-92. POLARITY1 Register ................13-93. POLARITY1 Register Field Descriptions ......................13-94. TYPE0 Register ..................13-95. TYPE0 Register Field Descriptions SPRUH82C – April 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 60 15-1. ECAP Initialization for CAP Mode Absolute Time, Rising Edge Trigger ......15-2. ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger List of Tables SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 61 16-22. EPWMx Run Time Changes for ....................16-23. EPWMx Initialization for ..................16-24. EPWMx Run Time Changes for ................. 16-25. Dead-Band Generator Submodule Registers SPRUH82C – April 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 62 16-72. Trip-Zone Submodule Select Register (TZSEL) Field Descriptions ............. 16-73. Trip-Zone Control Register (TZCTL) Field Descriptions ..........16-74. Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions List of Tables SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 63 17-34. EDMA3CC Error Register (CCERR) Field Descriptions ..........17-35. EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions ..............17-36. Error Evaluate Register (EEVAL) Field Descriptions SPRUH82C – April 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 64 17-84. Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) Field Descriptions ..17-85. Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF) Field Descriptions List of Tables SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 65 18-38. Transmit Revision ID Register (TXREVID) Field Descriptions ............18-39. Transmit Control Register (TXCONTROL) Field Descriptions ..........18-40. Transmit Teardown Register (TXTEARDOWN) Field Descriptions SPRUH82C – April 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 66 19-1. EMIFA Pins Used to Access Both SDRAM and Asynchronous Memories ..................19-2. EMIFA Pins Specific to SDRAM ..............19-3. EMIFA Pins Specific to Asynchronous Memory List of Tables SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 67 19-50. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions ............19-51. SDRAM Configuration Register (SDCR) Field Descriptions ........... 19-52. SDRAM Refresh Control Register (SDRCR) Field Descriptions SPRUH82C – April 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 68 21-15. Host Port Interface Write Address Register (HPIAW) Field Descriptions .......... 21-16. Host Port Interface Read Address Register (HPIAR) Field Descriptions List of Tables SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 69 23-20. LCD Raster Timing Register 0 (RASTER_TIMING_0) Field Descriptions 1064 ........23-21. LCD Raster Timing Register 1 (RASTER_TIMING_1) Field Descriptions 1066 SPRUH82C – April 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 70 24-43. Transmit Clock Check Control Register (XCLKCHK) Field Descriptions 1181 ........24-44. Transmitter DMA Event Control Register (XEVTCTL) Field Descriptions 1182 List of Tables SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 71 26-2. MMC/SD Mode Write Sequence 1271 ..................26-3. MMC/SD Mode Read Sequence 1272 ................. 26-4. Description of MMC/SD Interrupt Requests 1282 SPRUH82C – April 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 72 27-22. Scratch Registers (SCRATCHn) Field Descriptions 1342 ................. 27-23. Kick Registers (KICKnR) Field Descriptions 1342 .................... 28-1. MPY Bit Field of P0PHYCR 1348 List of Tables SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 73 ............ 29-10. SPI Global Control Register 1 (SPIGCR1) Field Descriptions 1442 ..............29-11. SPI Interrupt Register (SPIINT0) Field Descriptions 1444 SPRUH82C – April 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 74 31-6. UART Registers 1515 ..............31-7. Receiver Buffer Register (RBR) Field Descriptions 1516 ............31-8. Transmitter Holding Register (THR) Field Descriptions 1517 List of Tables SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 75 32-31. uPP DMA Channel Q Descriptor 2 Register (UPID2) Field Descriptions 1577 ........... 32-32. uPP DMA Channel Q Status 0 Register (UPQS0) Field Descriptions 1578 SPRUH82C – April 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 76 34-22. Host Buffer Descriptor Word 6 (HBD Word 6) 1655 ............... 34-23. Host Buffer Descriptor Word 7 (HBD Word 7) 1655 List of Tables SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 77 ............34-71. Receive Count Register (RXCOUNT) Field Descriptions 1725 ..........34-72. Type Register (Host mode only) (HOST_TYPE0) Field Descriptions 1726 SPRUH82C – April 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 78 34-120. Queue Manager Queue N Status Register B (QSTATB[N]) Field Descriptions 1756 ....... 34-121. Queue Manager Queue N Status Register C (QSTATC[N]) Field Descriptions 1757 List of Tables SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 79 35-44. Channel n Bottom Field Vertical Ancillary Position Register (CnBVANCPOS) Field Descriptions 1817 ....35-45. Channel n Bottom Field Vertical Ancillary Size Register (CnBVANCSIZE) Field Descriptions 1818 SPRUH82C – April 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 80: Preface
A legend explains the notation used for the properties. – Reserved bits in a register figure designate a bit that is used for future device expansion. Code Composer Studio is a trademark of Texas Instruments. ARM926EJ-S, Jazelle are trademarks of ARM Limited.
Page 81: Overview
Chapter 1 SPRUH82C – April 2013 – Revised September 2016 Overview ........................... Topic Page ....................... Introduction ....................ARM Subsystem SPRUH82C – April 2013 – Revised September 2016 Overview Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 82: Introduction
Introduction www.ti.com Introduction The AM1808/AM1810 ARM microprocessor contains an ARM RISC CPU for general-purpose processing and systems control. The AM1808/AM1810 ARM microprocessor consists of the following primary components: • ARM subsystem and associated memories • A set of I/O peripherals •...
Page 83: Arm Subsystem
Operating States/Modes ................. Processor Status Registers ............... Exceptions and Exception Vectors .................. The 16-BIS/32-BIS Concept ................... 16-BIS/32-BIS Advantages ..................Co-Processor 15 (CP15) SPRUH82C – April 2013 – Revised September 2016 ARM Subsystem Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 84: Introduction
The RAM/ROM locations are not accessible by any other master peripherals. Furthermore, the ARM has DMA and CFG bus master ports via the AHB interface. ARM Subsystem SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 85: Operating States/Modes
Bit 28 - V bit: Overflow or underflow NOTE: See the Programmer’s Model of the ARM926EJ-S Technical Reference Manual (TRM), downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information. SPRUH82C – April 2013 – Revised September 2016 ARM Subsystem Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 86: Exceptions And Exception Vectors
Undefined instruction Undefined Unchanged Software interrupt Supervisor Unchanged Pre-fetch abort Abort Unchanged Data abort Abort Unchanged Reserved — — — Unchanged ARM Subsystem SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 87: The 16-Bis/32-Bis Concept
Various portions of a system can be optimized for speed or for code density by switching between 16-BIS and 32-BIS execution, as appropriate. SPRUH82C – April 2013 – Revised September 2016 ARM Subsystem Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 88: Co-Processor 15 (Cp15)
Lockdown of TLB entries, using CP15 register 10 NOTE: See the Memory Management Unit of the ARM926EJ-S Technical Reference Manual (TRM), downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information. ARM Subsystem SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 89: Caches And Write Buffer
NOTE: See the Caches and Write Buffer of the ARM926EJ-S Technical Reference Manual (TRM), downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information. SPRUH82C – April 2013 – Revised September 2016 ARM Subsystem Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 90: System Interconnect
Chapter 3 SPRUH82C – April 2013 – Revised September 2016 System Interconnect ........................... Topic Page ....................... Introduction ..............System Interconnect Block Diagram System Interconnect SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 91: Introduction
EMAC, HPI, LCDC, PRU subsystems, USBs, uPP, SATA, and VPIF. Not all master peripherals may connect to all slave peripherals. The supported connections are designated by an X in Table 3-1. Table 3-1. AM1808/AM1810 ARM Microprocessor System Interconnect Matrix Masters Slaves Default...
Page 92: System Interconnect Block Diagram
Timer64P3 Asynchronous Bridge BR F5 SCR F8 eCAP0 eCAP1 Paths with dashed lines cross the subchip boundary eCAP2 SPI1 EDMA3_0_CC0 EDMA3_0_CC0 System Interconnect SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 93: System Memory
Chapter 4 SPRUH82C – April 2013 – Revised September 2016 System Memory ........................... Topic Page ....................... Introduction ....................ARM Memories ......................Peripherals SPRUH82C – April 2013 – Revised September 2016 System Memory Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 94: Introduction
(PSC), and the system configuration module (SYSCFG). See the device- specific data manual for the complete list of peripherals supported on your device. System Memory SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 95: Memory Protection Unit (Mpu)
SPRUH82C – April 2013 – Revised September 2016 Memory Protection Unit (MPU) ........................... Topic Page ....................... Introduction ....................... Architecture ....................MPU Registers SPRUH82C – April 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 96: Introduction
(MPU_ADDR_ERR_INT) and a protection interrupt (MPU_PROT_ERR_INT). Figure 5-1. MPU Block Diagram Input Output Protection Data Data Checks MPU_ADDR_ERR_INT MMRs MPU_PROT_ERR_INT MPU Register Bus Memory Protection Unit (MPU) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 97: Mpu Default Configuration
In some cases, a particular setting depends on software being executed at the time of the access or the configuration of the master peripheral. SPRUH82C – April 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 98: Memory Protection Ranges
MPU. The MPU can be configured for assumed allowed or assumed disallowed mode as dictated by the ASSUME_ALLOWED bit in the configuration register (CONFIG). Memory Protection Unit (MPU) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 99: Permission Structures
Description Supervisor may read Supervisor may write Supervisor may execute User may read User may write User may execute SPRUH82C – April 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 100: Protection Check
5.2.7 Reset Considerations After reset, the memory protection page attribute registers (MPPA) default to 0. This disables all protection features. Memory Protection Unit (MPU) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 101: Interrupt Support
Boot configuration address error BOOTCFG_PROT_ERR Boot configuration protection error 5.2.9 Emulation Considerations Memory and MPU registers are not protected against emulation accesses. SPRUH82C – April 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 102: Mpu Registers
Fixed range end address register Section 5.3.8 01E1 5108h FXD_MPPA Fixed range memory protection page attributes register Section 5.3.9 Memory Protection Unit (MPU) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 103 Fault address register Section 5.3.13 01E1 5304h FLTSTAT Fault status register Section 5.3.14 01E1 5308h FLTCLR Fault clear register Section 5.3.15 SPRUH82C – April 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 104: Revision Identification Register (Revid)
Assume allowed. When an address is not covered by any MPU protection range, this bit determines whether the transfer is assumed to be allowed or not allowed. Assume is disallowed. Assume is allowed. Memory Protection Unit (MPU) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 105: Interrupt Raw Status/Set Register (Irawstat)
Protection violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the status; writing 0 has no effect. Interrupt is not set. Interrupt is set. SPRUH82C – April 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 106: Interrupt Enable Status/Clear Register (Ienstat)
If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0 has no effect. Interrupt is not set. Interrupt is set. Memory Protection Unit (MPU) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 107: Interrupt Enable Set Register (Ienset)
Writing 0 has no effect. Interrupt is cleared/disabled. PROTERR_CLR Protection violation error disable. Writing 0 has no effect. Interrupt is cleared/disabled. SPRUH82C – April 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 108: Fixed Range Start Address Register (Fxd_Mpsar)
Figure 5-10. Fixed Range End Address Register (FXD_MPEAR) Reserved LEGEND: R = Read only; -n = value after reset Memory Protection Unit (MPU) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 109: Fixed Range Memory Protection Page Attributes Register (Fxd_Mppa)
Access is allowed. User Write permission. Access is denied. Access is allowed. User Execute permission. Access is denied. Access is allowed. SPRUH82C – April 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 110: Programmable Range N Start Address Registers (Progn_Mpsar)
Table 5-16. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions Field Value Description 31-16 START_ADDR C000h–DFFFh Start address for range N. 15-0 Reserved Reserved Memory Protection Unit (MPU) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 111: Programmable Range N End Address Registers (Progn_Mpear)
Table 5-18. MPU2 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions Field Value Description 31-16 END_ADDR C000h–DFFFh Start address for range N. 15-0 Reserved FFFFh Reserved SPRUH82C – April 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 112: Programmable Range N Memory Protection Page Attributes Register (Progn_Mppa)
Access is allowed. User Write permission. Access is denied. Access is allowed. User Execute permission. Access is denied. Access is allowed. Memory Protection Unit (MPU) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 113: Fault Address Register (Fltaddrr)
Table 5-20. Fault Address Register (FLTADDRR) Field Descriptions Field Value Description 31-0 FLTADDR 0-FFFF FFFFh Memory address of fault. SPRUH82C – April 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 114: Fault Status Register (Fltstat)
Supervisor write fault. Reserved Relaxed cache write back fault. 13h-1Fh Reserved Supervisor read fault. 21h-3Eh Reserved Relaxed cache line fill fault. Memory Protection Unit (MPU) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 115: Fault Clear Register (Fltclr)
Reserved CLEAR Command to clear the current fault. Writing 0 has no effect. No effect. Clear the current fault. SPRUH82C – April 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 116: Device Clocking
SPRUH82C – April 2013 – Revised September 2016 Device Clocking ........................... Topic Page ......................Overview ..................Frequency Flexibility ..................Peripheral Clocking Device Clocking SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 117: Overview
PLL1_SYSCLK3 Not Applicable Not Applicable (not configured by default) ECAPs, UART1/2, Timer64P2/3, eHRPWMs, McBSPs, ASYNC3 Not Applicable Not Applicable McASP0, SPI1 SPRUH82C – April 2013 – Revised September 2016 Device Clocking Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 118: Overall Clocking Diagram
DDR2/mDDR clocking. Section 6.3.3 for EMIFA clocking. Section 6.3.4 for EMAC clocking. Section 6.3.5 for uPP clocking. Section 6.3.6 for McASP clocking. Device Clocking SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 119: Frequency Flexibility
PLLM setting of ×24 and a POSTDIV setting of /3, even though both of these modes would result in a CPU frequency of 200 MHz. SPRUH82C – April 2013 – Revised September 2016 Device Clocking Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 120: Peripheral Clocking
USB0PHY_PLLON bit is cleared to 0, the USB2.0 PHY is allowed to stop the 48 MHz clock during USB SUSPEND. Device Clocking SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 121: Usb Clocking Diagram
38.4, 13, 26, 20, or 40 MHz. The PLL inside the USB2.0 PHY can be configured to accept any of these input clock frequencies. USB_REFCLKIN must be 48 MHz. SPRUH82C – April 2013 – Revised September 2016 Device Clocking Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 122: Ddr2/Mddr Memory Controller Clocking
DDR2/mDDR memory controller via the LPSC while still providing a clock on the DDR_CLK and DDR_CLK. NOTE: DDR_CLK and DDR_CLK are output clock signals. Device Clocking SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 123: Ddr2/Mddr Memory Controller Clocking Diagram
264 MHz 132 MHz 504 MHz Div2 252 MHz 8000h 252 MHz 126 MHz Section 6.2 for explanation of POSTDIV divider modes. SPRUH82C – April 2013 – Revised September 2016 Device Clocking Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 124: Emifa Clocking
133 MHz 89 MHz 66.5 MHz Div4 100 MHz 89 MHz 100 MHz Section 6.2 for explanation of POSTDIV divider modes. Device Clocking SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 125: Emac Clocking
0000 1000 RMII_MHZ_50_CLK Signal NOTE: The SYSCLK7 output clock does not meet the RMII reference clock specification of 50 MHz +/-50 ppm. SPRUH82C – April 2013 – Revised September 2016 Device Clocking Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 126: Emac Reference Clock Frequencies
Not Applicable Section 6.2 for explanation of POSTDIV divider modes. Certain PLL configurations do not support a 50 MHz clock on PLL0_SYSCLK7. Device Clocking SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 127: Upp Clocking
CFGCHIP3[ASYNC3_CLKSRC] UPP_2xTXCLK pin Table 6-8. uPP Transmit Clock Selection CFGCHIP3.UPP_TX_CLKSRC bit CFGCHIP3.ASYNC3_CLKSRC bit uPP Transmit Clock Source PLL0_SYSCLK2 PLL1_SYSCLK2 UPP_2xTXCLK pin SPRUH82C – April 2013 – Revised September 2016 Device Clocking Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 128: Mcasp Clocking
Module PLL0_SYSCLK2 Clock LPSC McASP0 PLL1_SYSCLK2 TX/RX Reference Clock Clock Frame Sync PLL0_AUXCLK Generator Generator ACLKX AHCLKX AFSX AFSR ACLKR AHCLKR Device Clocking SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 129: I/O Domains
Peripheral Serial Clock EMAC PLL0_SYSCLK4 or RMII_MHZ_50_CLK PLL0_SYSCLK2 or Peripheral Serial Clock VPIF PLL0_SYSCLK2 or Peripheral Serial Clock USBs USB_REFCLKIN or AUXCLK SPRUH82C – April 2013 – Revised September 2016 Device Clocking Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 130: Phase-Locked Loop Controller (Pllc)
SPRUH82C – April 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) ........................... Topic Page ..................... Introduction ....................PLL Controllers ....................PLLC Registers Phase-Locked Loop Controller (PLLC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 131: Introduction
PLL mode operation (set the PLLEN bit in PLLCTL to 1). The PLL controller registers are listed in Section 7.3. SPRUH82C – April 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 132: Pllc Structure
PLLDIV3 (/3) SYSCLK3 POSTDIV PLLDIV1 (/1) SYSCLK1 PLLM DDR2/mDDR Internal Clock Source SYSCLK1 OSCDIV PLLC1 OBSCLK SYSCLK2 SYSCLK3 OCSEL[OCSRC] Phase-Locked Loop Controller (PLLC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 133: Device Clock Generation
The PLL0 input clock source can be configured to use PLL1_SYSCLK3 instead of OSCIN by programming the EXTCLKSRC bit in the PLLC0 PLL control register (PLLCTL). The PLL1 input clock source will also be OSCIN. SPRUH82C – April 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 134: Steps For Programming The Plls
4. Set the PLL_MASTER_LOCK bit in CFGCHIP0 and/or the PLL1_MASTER_LOCK bit in CFGCHIP3, as required. 5. Write an incorrect key value to the KICK0R and KICK1R registers. Phase-Locked Loop Controller (PLLC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 135 6. Wait for the PLL to lock. See the device-specific data manual for PLL lock time. 7. Set the PLLEN bit in PLLCTL to 1 (removes PLL from bypass mode). SPRUH82C – April 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 136: Pllc Registers
PLLC0 Emulation Performance Counter 0 Register Section 7.3.36 01C1 11F4h EMUCNT1 PLLC0 Emulation Performance Counter 1 Register Section 7.3.37 Phase-Locked Loop Controller (PLLC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 137: Pllc0 Revision Identification Register (Revid)
Table 7-4. PLLC0 Revision Identification Register (REVID) Field Descriptions Field Value Description 31-0 4481 3C00h Peripheral revision ID for PLLC0. SPRUH82C – April 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 138: Pllc1 Revision Identification Register (Revid)
Power On Reset (POR) was not the last reset to occur. Power On Reset (POR) was the last reset to occur. Phase-Locked Loop Controller (PLLC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 139: Pllc0 Reset Control Register (Rsctrl)
Register is locked when read value is 3h. Register is unlocked when read value is Ch. 5A69h RSCTRL unlock key SPRUH82C – April 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 140: Pllc0 Control Register (Pllctl)
PLL0 is operating. PLL0 is powered-down. PLLEN PLL0 mode enables. PLL0 is in bypass mode. PLL0 mode is enabled, not bypassed. Phase-Locked Loop Controller (PLLC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 141: Pllc1 Control Register (Pllctl)
PLL1 is operating. PLL1 is powered-down. PLLEN PLL1 mode enables. PLL1 is in bypass mode. PLL1 mode is enabled, not bypassed. SPRUH82C – April 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 142: Pllc0 Obsclk Select Register (Ocsel)
PLLC0 OBSCLK source. Output on CLKOUT pin. 0-13h Reserved OSCIN 15h-16h Reserved PLL0_SYSCLK1 PLL0_SYSCLK2 PLL0_SYSCLK3 PLL0_SYSCLK4 PLL0_SYSCLK5 PLL0_SYSCLK6 PLL0_SYSCLK7 PLLC1 OBSCLK Disabled Phase-Locked Loop Controller (PLLC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 143: Pllc1 Obsclk Select Register (Ocsel)
Description 31-5 Reserved Reserved OCSRC 0-1Fh PLLC1 OBSCLK source. 0-13h Reserved OSCIN 15h-16h Reserved PLL1_SYSCLK1 PLL1_SYSCLK2 PLL1_SYSCLK3 1A-1Fh Reserved SPRUH82C – April 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 144: Pll Multiplier Control Register (Pllm)
Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL pre-divide by 1). Phase-Locked Loop Controller (PLLC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 145: Pllc0 Divider 1 Register (Plldiv1)
Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1). SPRUH82C – April 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 146: Pllc0 Divider 2 Register (Plldiv2)
Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL divide by 2). Phase-Locked Loop Controller (PLLC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 147: Pllc0 Divider 3 Register (Plldiv3)
Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 2h (PLL divide by 3). SPRUH82C – April 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 148: Pllc0 Divider 4 Register (Plldiv4)
Reserved Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults 2 (PLL divide by 3). Phase-Locked Loop Controller (PLLC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 149: Pllc0 Divider 6 Register (Plldiv6)
Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 5 (PLL divide by 6). SPRUH82C – April 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 150: Pllc0 Oscillator Divider 1 Register (Oscdiv)
RATIO 0-1Fh Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1. Phase-Locked Loop Controller (PLLC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 151: Pll Post-Divider Control Register (Postdiv)
Table 7-27. PLL Controller Command Register (PLLCMD) Field Descriptions Field Value Description 31-1 Reserved Reserved GOSET GO bit for phase alignment. Clear bit (no effect) Phase alignment SPRUH82C – April 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 152: Pll Controller Status Register (Pllstat)
Status of GO operation. If 1, indicates GO operation is in progress. GO operation is not in progress. GO operation is in progress. Phase-Locked Loop Controller (PLLC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 153: Pllc0 Clock Align Control Register (Alnctl)
PLL0_SYSCLK2 needs to be aligned to others selected in this register. ALN1 PLL0_SYSCLK1 needs to be aligned to others selected in this register. SPRUH82C – April 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 154: Pllc1 Clock Align Control Register (Alnctl)
PLL1_SYSCLK2 needs to be aligned to others selected in this register. ALN1 PLL1_SYSCLK1 needs to be aligned to others selected in this register. Phase-Locked Loop Controller (PLLC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 155: Pllc0 Plldiv Ratio Change Status Register (Dchange)
Ratio is not modified. Ratio is modified. SYS1 PLL0_SYSCLK1 divide ratio is modified. Ratio is not modified. Ratio is modified. SPRUH82C – April 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 156: Pllc1 Plldiv Ratio Change Status Register (Dchange)
Ratio is not modified. Ratio is modified. SYS1 PLL1_SYSCLK1 divide ratio is modified. Ratio is not modified. Ratio is modified. Phase-Locked Loop Controller (PLLC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 157: Pllc0 Clock Enable Control Register (Cken)
PLLC1 OBSCLK is enabled. For PLLC1 OBSCLK to toggle, both the OBSEN bit and the OD1EN bit in the PLLC1 oscillator divider 1 register (OSCDIV) must be set to 1. Reserved Reserved SPRUH82C – April 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 158: Pllc0 Clock Status Register (Ckstat)
AUXCLK on status. PLLC0 AUXCLK is controlled by the AUXEN bit in the PLLC0 clock enable control register (CKEN). PLLC0 AUXCLK is off. PLLC0 AUXCLK is on. Phase-Locked Loop Controller (PLLC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 159: Pllc1 Clock Status Register (Ckstat)
OBSEN bit in the PLLC1 clock enable control register (CKEN). PLLC1 OBSCLK is off. PLLC1 OBSCLK is on. Reserved Reserved SPRUH82C – April 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 160: Pllc0 Sysclk Status Register (Systat)
PLL0_SYSCLK5 on status. SYS4ON PLL0_SYSCLK4 on status. SYS3ON PLL0_SYSCLK3 on status. SYS2ON PLL0_SYSCLK2 on status. SYS1ON PLL0_SYSCLK1 on status. Phase-Locked Loop Controller (PLLC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 161: Pllc1 Sysclk Status Register (Systat)
Table 7-38. PLLC1 SYSCLK Status Register (SYSTAT) Field Descriptions Field Value Description 31-3 Reserved Reserved SYS3ON PLL1_SYSCLK3 on status. SYS2ON PLL1_SYSCLK2 on status. SYS1ON PLL1_SYSCLK1 on status. SPRUH82C – April 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 162: Emulation Performance Counter 0 Register (Emucnt0)
Table 7-40. Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions Field Value Description 31-0 COUNT 0-FFFF FFFFh Counter value for upper 64-bits. Phase-Locked Loop Controller (PLLC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 163: Power And Sleep Controller (Psc)
Power Domain and Module Topology ................Executing State Transitions ..............IcePick Emulation Support in the PSC ....................PSC Interrupts ....................PSC Registers SPRUH82C – April 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 164: Introduction
Timer64P0/P1, and I2C0); from a power savings stand point, clock-gating these peripherals does not result in significant power savings. Power and Sleep Controller (PSC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 165: Psc0 Default Module Configuration
AlwaysON (PD0) SwRstDisable — 22-23 Not Used — — — Note that the SATA module requires forced state transitions. SPRUH82C – April 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 166: Power Domain States
Both PD0 and PD1 power domains in PSC0 and PSC1 are powered by the CVDD pins of the device. There is no capability to individually remove voltage/power from the on-chip RAM power domains. Power and Sleep Controller (PSC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 167: Module States
2. Set the LRST bit in the module control register (MDCTLn) to 1 to de-assert module’s local reset. If the CPU is in the enable state, it immediately executes program instructions after reset is de-asserted. SPRUH82C – April 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 168: Module States
See Section 8.2.2.1 for additional considerations, constraints, limitations around this mode. Power and Sleep Controller (PSC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 169: Executing State Transitions
4. Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. The modules are safely in the new states only after the GOSTAT[x] bit in PTSTAT is cleared to 0. SPRUH82C – April 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 170: Icepick Emulation Support In The Psc
NEXT bit in the MDCTL/PDCTL registers. IcePick support only applies to the modules listed in Section 8.4; therefore, the PSC interrupt conditions only apply to those modules listed. Power and Sleep Controller (PSC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 171: Interrupt Registers
Set the ALLEV bit in the INTEVAL before exiting your PSC interrupt service routine to ensure that you do not miss any PSC interrupts. SPRUH82C – April 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 172: Interrupt Handling
(d) Set the ALLEV bit in INTEVAL. Setting this bit reasserts the PSC interrupt to the device interrupt controller, if there are still any active interrupt events. Power and Sleep Controller (PSC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 173: Psc Registers
Section 8.6.17 01E2 787Ch MDSTAT31 01E2 7A00h- MDCTL0- Module Control n Register (modules 0-31) Section 8.6.19 01E2 7A7Ch MDCTL31 SPRUH82C – April 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 174: Revision Identification Register (Revid)
Evaluate PSC interrupt (PSCn_ALLINT). A write of 0 has no effect. A write of 1 re-evaluates the interrupt condition. Power and Sleep Controller (PSC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 175: Psc0 Module Error Pending Register 0 (Modules 0-15) (Merrpr0)
Figure 8-4. PSC1 Module Error Pending Register 0 (MERRPR0) Reserved LEGEND: R = Read only; -n = value after reset SPRUH82C – April 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 176: Psc0 Module Error Clear Register 0 (Modules 0-15) (Merrcr0)
Figure 8-6. PSC1 Module Error Clear Register 0 (MERRCR0) Reserved LEGEND: R = Read only; -n = value after reset Power and Sleep Controller (PSC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 177: Power Error Pending Register (Perrpr)
A write of 1 clears the P bit in PERRPR and the interrupt status bits in PDSTAT1. Reserved Reserved SPRUH82C – April 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 178: Power Domain Transition Command Register (Ptcmd)
MDCTL.NEXT for all the modules residing on this domain). If any of the NEXT fields are not matching the corresponding current state (MDSTAT.STATE), the PSC will transition those respective domain/modules to the new NEXT state. Power and Sleep Controller (PSC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 179: Power Domain Transition Status Register (Ptstat)
No transition in progress. Modules in Always ON power domain are transitioning. Always On power domain is transitioning. SPRUH82C – April 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 180: Power Domain 0 Status Register (Pdstat0)
Power domain is in the off state. Power domain is in the on state. 2h-Fh Reserved 10h-1Ah Power domain is in transition. 1Bh-1Fh Reserved Power and Sleep Controller (PSC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 181: Power Domain 1 Status Register (Pdstat1)
Power domain is in the off state. Power domain is in the on state. 2h-Fh Reserved 10h-1Ah Power domain is in transition. 1Bh-1Fh Reserved SPRUH82C – April 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 182: Power Domain 0 Control Register (Pdctl0)
Power domain next state. For Always ON power domain this bit is read/write, but writes have no effect since internally this power domain always remains in the on state. Power domain off. Power domain on. Power and Sleep Controller (PSC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 183: Power Domain 1 Control Register (Pdctl1)
Enable interrupt. Reserved Reserved Reserved Reserved NEXT User-desired power domain next state. Power domain off. Power domain on. SPRUH82C – April 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 184: Power Domain 0 Configuration Register (Pdcfg0)
RAM power domain. ALWAYSON Always ON power domain. Not an Always ON power domain. Always ON power domain. Power and Sleep Controller (PSC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 185: Power Domain 1 Configuration Register (Pdcfg1)
RAM power domain. ALWAYSON Always ON power domain. Not an Always ON power domain. Always ON power domain. SPRUH82C – April 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 186: Module Status N Register (Mdstatn)
Module state status: indicates current module status. SwRstDisable state SyncReset state Disable state Enable state 4h-3Fh Indicates transition Power and Sleep Controller (PSC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 187: Psc0 Module Control N Register (Modules 0-15) (Mdctln)
De-assert local reset Reserved Reserved NEXT 0-3h Module next state. SwRstDisable state SyncReset state Disable state Enable state SPRUH82C – April 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 188: Psc1 Module Control N Register (Modules 0-31) (Mdctln)
Force is enabled. 30-3 Reserved Reserved NEXT 0-3h Module next state. SwRstDisable state SyncReset state Disable state Enable state Power and Sleep Controller (PSC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 189: Power Management
....................RTC-Only Mode ..........Dynamic Voltage and Frequency Scaling (DVFS) ....................Deep Sleep Mode ........9.10 Additional Peripheral Power Management Considerations SPRUH82C – April 2013 – Revised September 2016 Power Management Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 190: Introduction
(PSC) chapter. For detailed information on the PLLC0 and PLLC1, see the Device Clocking chapter and the Phase-Locked Loop Controller (PLLC) chapter. Power Management SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 191: Features
Internal pull-up and pull- The internal pull-ups and pull-downs are Reduces the I/O leakage power. down resistor control enabled/disabled by groups. SPRUH82C – April 2013 – Revised September 2016 Power Management Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 192: Clock Management
PLL lock time when switching back to a normal operating level. The Device Clocking chapter and the Phase-Locked Loop Controller (PLLC) chapter describe PLL bypass and PLL power down. Power Management SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 193: Arm Sleep Mode Management
GPIO or watchdog timer) must not be disabled, or the device will never wake up. For more information on this sleep mode, see the ARM926EJ-S Technical Reference Manual (TRM), downloadable from http://infocenter.arm.com/help/index.jsp. SPRUH82C – April 2013 – Revised September 2016 Power Management Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 194: Arm Clock Off
ARM (to exit the wait-for- interrupt mode). This example assumes that the ARM enabled this interrupt before entering its wait-for-interrupt sleep mode state. Power Management SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 195: Rtc-Only Mode
Changing the SYSCLK frequency through the dividers is faster as there is no need to reprogram the PLL. However, the SYSCLK frequency will depend solely on the divider ratios used. SPRUH82C – April 2013 – Revised September 2016 Power Management Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 196: Voltage Scaling Considerations
(RTC). The DEEPSLEEP pin cannot be driven by both an external controller and its internal real-time clock at the same time. Power Management SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 197: Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up
6. Configure the desired states to the peripherals and enable as required. For more details on the clock enable procedure of the DDR2/mDDR memory controller, see the DDR2/mDDR Memory Controller chapter. SPRUH82C – April 2013 – Revised September 2016 Power Management Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 198: Entering/Exiting Deep Sleep Mode Using Rtc Controlled Wake-Up
6. Configure the desired states to the peripherals and enable as required. For more details on the clock enable procedure of the DDR2/mDDR memory controller, see the DDR2/mDDR Memory Controller chapter. Power Management SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 199: Deep Sleep Sequence
Figure 9-1. Deep Sleep Mode Sequence See Note: SLEEPENABLE (internal) DEEPSLEEP CLKGATE (internal) PLLC Ref Clk (internal) OSC_GZ (internal) OSCIN SLEEPCOMPLETE (internal) SPRUH82C – April 2013 – Revised September 2016 Power Management Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 200: Entering/Exiting Deep Sleep Mode Using Software Handshaking
NOTE: If the USB1.1 subsystem is used and the 48 MHz clock input is sourced from the USB2.0 PHY, then the USB2.0 PHY should not be powered down. Power Management SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 201: Ddr2/Mddr Memory Controller Clock Gating And Self-Refresh Mode
In the event that certain receivers are not used (such as in a low-power state), they can be disabled to conserve power. SPRUH82C – April 2013 – Revised September 2016 Power Management Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 202: Pull-Up/Pull-Down Disable
Internal resistors are disabled through the pullup/pulldown enable register (PUPD_ENA) in the System Configuration (SYSCFG) Module chapter. Power Management SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 203: System Configuration (Syscfg) Module
..................... 10.1 Introduction ......................10.2 Protection ..................10.3 Master Priority Control ....................10.4 Interrupt Support .................... 10.5 SYSCFG Registers SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 204: Introduction
Supervisor mode. The registers that can only be accessed in privileged mode are listed in Section 10.5. See the ARM926EJ-S Technical Reference Manual (TRM), downloadable from http://infocenter.arm.com/help/index.jsp for details on privilege levels. System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 205: Kicker Mechanism Protection
EDMA3_0_TC0 - read EDMA3_0_TC0 - write EDMA3_0_TC1 - read EDMA3_0_TC1 - write EDMA3_1_TC0 – read EDMA3_1_TC0 – write 22-33 Reserved SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 206: Default Master Priority
You should reconfigure the LCDC priority to the highest or equal to other high-priority masters in an application to ensure that the throughput/latency requirements for the LCDC are met. System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 207: Interrupt Support
Section 10.5.9.3 01C1 4120h PINMUX0 Pin Multiplexing Control 0 Register Privileged mode Section 10.5.10.1 This register is for internal-use only. SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 208: System Configuration Module 1 (Syscfg1) Registers
RXACTIVE RXACTIVE Control Register Privileged mode Section 10.5.24 01E2 C018h PWRDN Power Down Control Register Privileged mode Section 10.5.25 System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 209: Revision Identification Register (Revid)
LEGEND: R = Read only; -n = value after reset Table 10-6. Device Identification Register 0 (DEVIDR0) Field Descriptions Field Value Description 31-0 DEVID0 1B7D 102Fh Device identification. SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 210: Boot Configuration Register (Bootcfg)
Field Value Description 31-6 Reserved Reserved CHIPREVID Identifies silicon revision of device. 0-3h Older silicon revision Silicon revision 2.2 System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 211: Kick Registers (Kick0R-Kick1R)
MMRs. The written data must be 95A4 F1E0h to unlock this register. KICK0R must be written before writing to the kick1 register. Writing any other value will lock the other MMRs. SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 212: Host 0 Configuration Register (Host0Cfg)
ARM boot ready bit allowing ARM to boot. ARM held in reset mode. ARM released from wait in reset mode. System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 213: Interrupt Registers
Indicates the interrupt is not set. Writing 0 has no effect. Indicates the interrupt is set. Writing 1 sets the status. SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 214: Interrupt Enable Status/Clear Register (Ienstat)
Indicates the interrupt is not set. Writing 0 has no effect. Indicates the interrupt is set. Writing 1 clears the status. System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 215: Interrupt Enable Register (Ienset)
Writing a 1 clears/disables this interrupt. PROTERR_CLR Protection violation error. Writing a 0 has not effect. Writing a 1 clears/disables this interrupt. SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 216: Fault Registers
Table 10-17. Fault Address Register (FLTADDRR) Field Descriptions Field Value Description 31-0 FLTADDR 0-FFFF FFFFh Fault address for the first fault transfer. System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 217: Fault Status Register (Fltstat)
User read fault 5h-7h Reserved Supervisor execute fault 9h-Fh Reserved Supervisor write fault 11h-1Fh Reserved Supervisor read fault 21h-3Fh Reserved SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 218: Master Priority Registers (Mstpri0-Mstpri2)
ARM_I 0-7h ARM_I port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest). System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 219: Master Priority 1 Register (Mstpri1)
PRU0 0-7h PRU0 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest). SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 220: Master Priority 2 Register (Mstpri2)
EMAC 0-7h EMAC port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest). System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 221: Pin Multiplexing Control Registers (Pinmux0-Pinmux19)
5h-7h Reserved Selects Function GP0[9] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 222 ACLKR/PRU0_R30[20]/GP0[15]/PRU0_R31[22] Control Selects Function PRU0_R31[22] Selects Function ACLKR 2h-3h Reserved Selects Function PRU0_R30[20] 5h-7h Reserved Selects Function GP0[15] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 223: Pin Multiplexing Control 1 Register (Pinmux1)
Selects Function GP0[3] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 224 Pin is 3-stated. Selects Function AXR15 Selects Function EPWM0TZ[0] Reserved Selects Function ECAP2_APWM2 5h-7h Reserved Selects Function GP0[7] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 225: Pin Multiplexing Control 2 Register (Pinmux2)
Selects Function MII_TXD[2] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 226 Selects Function PRU0_R31[7] Selects Function AXR7 Selects Function EPWM1TZ[0] Reserved Selects Function PRU0_R30[17] 5h-7h Reserved Selects Function GP1[15] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 227: Pin Multiplexing Control 3 Register (Pinmux3)
Selects Function MII_RXD[2] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 228 Pin is 3-stated. Selects Function SPI0_CLK Selects Function EPWM0A Reserved Selects Function GP1[8] 5h-7h Reserved Selects Function MII_RXCLK 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 229: Pin Multiplexing Control 4 Register (Pinmux4)
Selects Function GP1[2] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 230 Selects Function TM64P0_IN12 Selects Function SPI0_SCS[1] Selects Function TM64P0_OUT12 Reserved Selects Function GP1[7] 5h-7h Reserved Selects Function MDIO_CLK 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 231: Pin Multiplexing Control 5 Register (Pinmux5)
Selects Function GP2[12] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 232 Selects Function TM64P2_IN12 Selects Function SPI1_SCS[1] Selects Function EPWM1A Reserved Selects Function PRU0_R30[8] 5h-7h Reserved Selects Function GP2[15] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 233: Pin Multiplexing Control 6 Register (Pinmux6)
Selects Function GP2[4] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 234 EMA_CLK/PRU0_R30[5]/GP2[7]/PRU0_R31[5] Control Selects Function PRU0_R31[5] Selects Function EMA_CLK 2h-3h Reserved Selects Function PRU0_R30[5] 5h-7h Reserved Selects Function GP2[7] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 235: Pin Multiplexing Control 7 Register (Pinmux7)
Selects Function GP3[12] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 236 Selects Function GP3[14] 9h-Fh Reserved PINMUX7_3_0 EMA_CS[2]/GP3[15] Control Pin is 3-stated. Selects Function EMA_CS[2] 2h-7h Reserved Selects Function GP3[15] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 237: Pin Multiplexing Control 8 Register (Pinmux8)
Selects Function GP3[4] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 238 Selects Function GP3[6] 9h-Fh Reserved PINMUX8_3_0 EMA_D[15]/GP3[7] Control Pin is 3-stated. Selects Function EMA_D[15] 2h-7h Reserved Selects Function GP3[7] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 239: Pin Multiplexing Control 9 Register (Pinmux9)
Selects Function GP4[12] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 240 Selects Function GP4[14] 9h-Fh Reserved PINMUX9_3_0 EMA_D[7]/GP4[15] Control Pin is 3-stated. Selects Function EMA_D[7] 2h-7h Reserved Selects Function GP4[15] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 241: Pin Multiplexing Control 10 Register (Pinmux10)
Selects Function GP4[2] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 242 Selects Function MMCSD0_CLK Reserved Selects Function PRU1_R30[31] 5h-7h Reserved Selects Function GP4[7] 9h-Fh Reserved 10.5.10.12 Pin Multiplexing Control 11 Register (PINMUX11) System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 243: Pin Multiplexing Control 11 Register (Pinmux11)
Selects Function GP5[11] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 244 Selects Function PRU1_R31[23] Selects Function EMA_A[15] Selects Function MMCSD0_DAT[6] Reserved Selects Function PRU1_R30[23] 5h-7h Reserved Selects Function GP5[15] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 245: Pin Multiplexing Control 12 Register (Pinmux12)
Selects Function GP5[4] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 246 EMA_A[7]/PRU1_R30[15]/GP5[7] Control Pin is 3-stated. Selects Function EMA_A[7] 2h-3h Reserved Selects Function PRU1_R30[15] 5h-7h Reserved Selects Function GP5[7] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 247: Pin Multiplexing Control 13 Register (Pinmux13)
Selects Function GP6[10] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 248 Selects Function UHPI_HAS Reserved Selects Function PRU1_R30[14] 5h-7h Reserved Selects Function GP6[15] 9h-Fh Reserved 10.5.10.15 Pin Multiplexing Control 14 Register (PINMUX14) System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 249: Pin Multiplexing Control 14 Register (Pinmux14)
5h-7h Reserved Selects Function RMII_RXD[1] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 250 Selects Function UHPI_HCS Reserved Selects Function PRU1_R30[10] 5h-7h Reserved Selects Function GP6[7] 9h-Fh Reserved 10.5.10.16 Pin Multiplexing Control 15 Register (PINMUX15) System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 251: Pin Multiplexing Control 15 Register (Pinmux15)
5h-7h Reserved Selects Function PRU0_R30[12] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 252 Selects Function PRU1_R31[29] Selects Function VP_DIN[0] Selects Function UHPI_HD[8] Reserved Selects Function UPP_D[8] 5h-7h Reserved Selects Function RMII_CRS_DV 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 253 RMII_MHZ_50_CLK pin. Note that the SYSCLK7 output clock does not meet the RMII reference clock specification of 50 MHz +/-50 ppm. See Section 6.3.4 for more information. 9h-Fh Reserved SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 254: Pin Multiplexing Control 16 Register (Pinmux16)
5h-7h Reserved Selects Function GP7[12] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 255 Selects Function UHPI_HD[1] Reserved Selects Function UPP_D[1] 5h-7h Reserved Selects Function PRU0_R30[9] 9h-Fh Reserved 10.5.10.18 Pin Multiplexing Control 17 Register (PINMUX17) SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 256: Pin Multiplexing Control 17 Register (Pinmux17)
5h-7h Reserved Selects Function GP7[4] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 257 Selects Function LCD_D[1] Reserved Selects Function UPP_XD[9] 5h-7h Reserved Selects Function GP7[9] 9h-Fh Reserved 10.5.10.19 Pin Multiplexing Control 18 Register (PINMUX18) SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 258: Pin Multiplexing Control 18 Register (Pinmux18)
Selects Function GP8[12] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 259 Selects Function BOOT[1] Selects Function VP_DOUT[9] Selects Function LCD_D[9] Reserved Selects Function UPP_XD[1] 5h-7h Reserved Selects Function GP7[1] 9h-Fh Reserved SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 260: Pin Multiplexing Control 19 Register (Pinmux19)
5h-7h Reserved Selects Function GP6[2] 9h-Fh Reserved I = Input, O = Output, I/O = Bidirectional, X = Undefined System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 261 Selects Function PRU1_R31[6] Selects Function MMCSD1_DAT[5] Selects Function LCD_HSYNC Reserved Selects Function PRU1_R30[5] 5h-7h Reserved Selects Function GP8[9] 9h-Fh Reserved SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 262: Suspend Source Register (Suspsrc)
No emulation suspend. SPI0SRC SPI0 Emulation Suspend Source. ARM is the source of the emulation suspend. No emulation suspend. System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 263 No emulation suspend. TIMER64P_3SRC Timer3 64 Emulation Suspend Source. ARM is the source of the emulation suspend. No emulation suspend. SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 264 No emulation suspend. ECAP0SRC ECAP0 Emulation Suspend Source. ARM is the source of the emulation suspend. No emulation suspend. System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 265: Chip Signal Register (Chipsig)
No effect Asserts interrupt CHIPSIG1 Asserts SYSCFG_CHIPINT1 interrupt. No effect Asserts interrupt CHIPSIG0 Asserts SYSCFG_CHIPINT0 interrupt. No effect Asserts interrupt SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 266: Chip Signal Clear Register (Chipsig_Clr)
No effect Clears interrupt CHIPSIG1 Clears SYSCFG_CHIPINT1 interrupt. No effect Clears interrupt CHIPSIG0 Clears SYSCFG_CHIPINT0 interrupt. No effect Clears interrupt System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 267: Chip Configuration 0 Register (Cfgchip0)
16 bytes 32 bytes 64 bytes Reserved EDMA30TC0DBS EDMA3_0_TC0 Default Burst Size (DBS). 16 bytes 32 bytes 64 bytes Reserved SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 268: Chip Configuration 1 Register (Cfgchip1)
R/W-0 R/W-0 Reserved AMUTESEL0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 269: Chip Configuration 1 Register (Cfgchip1) Field Descriptions
EMAC C2 RX Threshold Pulse Interrupt EMAC C2 RX Pulse Interrupt EMAC C2 TX Pulse Interrupt EMAC C2 Miscellaneous Interrupt 13h-1Fh Reserved SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 270 GPIO Interrupt from Bank 4 GPIO Interrupt from Bank 5 GPIO Interrupt from Bank 6 GPIO Interrupt from Bank 7 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 271: Chip Configuration 2 Register (Cfgchip2)
USB2.0 PHY operation state control. USB2.0 PHY is enabled and is in operating state (normal operation). USB2.0 PHY is disabled and powered down. SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 272 12 MHz 24 MHz 48 MHz 19.2 MHz 38.4 MHz 13 MHz 26 MHz 20 MHz 40 MHz Ah-Fh Reserved System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 273: Chip Configuration 3 Register (Cfgchip3)
Clock source for ASYNC3. Clock driven by PLL0_SYSCLK2. Clock driven by PLL1_SYSCLK2. PRUEVTSEL PRU event input select. Normal mode Alternate mode SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 274: Chip Configuration 4 Register (Cfgchip4)
Reserved. Write the default value to all bits when modifying this register. AMUTECLR0 Clears the latched GPIO interrupt for AMUTEIN of McASP0 when set to 1. No effect Clears interrupt System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 275: Vtp I/O Control Register (Vtpio_Ctl)
VTP power down. Power down the VTP controller. The PWRSAVE bit setting is only valid when the POWERDN bit is cleared to 0. Disable power down. Enable power down. SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 276 Drive strength control bit. 0-5h Reserved 100% drive strength Reserved Digital filter control bit. 0-6h Reserved Digital filter is enabled. System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 277: Ddr Slew Register (Ddr_Slew)
Slew rate mode control status for command macro. Slew rate control is not supported on this device. Slew rate control is off. 1h-3h Reserved SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 278: Deep Sleep Register (Deepsleep)
Deep sleep counter. Number of cycles to count prior to the oscillator being stable. All 16 bits are tied directly to the counter in the Deep Sleep logic. System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 279: Pullup/Pulldown Enable Register (Pupd_Ena)
(PUPD_ENA). Internal pull-down functionality for pin group n is disabled. Internal pull-up functionality for pin group n is enabled. SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 280: Pullup/Pulldown Select Register (Pupd_Sel) Default Values
Pin Group CP[1] is configured for pull-up by default. PUPDSEL[0] Pin Group CP[0] is configured for pull-up by default. System Configuration (SYSCFG) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 281: Rxactive Control Register (Rxactive)
Power down feature disabled (SATA clock input circuitry is enabled). Power down feature enabled (SATA clock input circuitry is disabled). SPRUH82C – April 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 282: Arm Interrupt Controller (Aintc)
ARM Interrupt Controller (AINTC) ........................... Topic Page ..................... 11.1 Introduction ..................... 11.2 Interrupt Mapping ..................11.3 AINTC Methodology ....................11.4 AINTC Registers ARM Interrupt Controller (AINTC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 283: Aintc Interrupt Mapping
Intr 1 Channel 1 Channel 2 Intr (n–1) Peripheral Z Intr n Channel m n ≤ 100 m ≤ 31 SPRUH82C – April 2013 – Revised September 2016 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 284: Aintc System Interrupt Assignments
GPIO Bank 1 Interrupt GPIO_B2INT GPIO Bank 2 Interrupt GPIO_B3INT GPIO Bank 3 Interrupt GPIO_B4INT GPIO Bank 4 Interrupt ARM Interrupt Controller (AINTC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 285 Combined Interrupt VPIF_ALLINT VPIF Combined Interrupt EDMA3_1_CC0_INT0 EDMA3_1 Channel Controller 0 Shadow Region 0 Transfer Completion Interrupt SPRUH82C – April 2013 – Revised September 2016 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 286: Flow Of System Interrupts To Host
Conversion of polarity to active high • Conversion of interrupt type to pulse interrupts After the processing block, all interrupts will be active-high pulses. ARM Interrupt Controller (AINTC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 287: Interrupt Enabling
When multiple channels are mapped to the same host interrupt, then prioritization is done to select which interrupt is in the highest-priority channel and which should be sent first to the host. SPRUH82C – April 2013 – Revised September 2016 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 288: Interrupt Prioritization
(HINLR1 and HINLR2) display and control the nesting level for each host interrupt. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt. ARM Interrupt Controller (AINTC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 289: Interrupt Vectorization
ISR null address. When there is a pending interrupt then the ISR address is calculated as exact base + offset for that interrupt number. SPRUH82C – April 2013 – Revised September 2016 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 290: Interrupt Status Clearing
System Interrupt Enable Clear Register 2 Section 11.4.29 FFFE E388h ECR3 System Interrupt Enable Clear Register 3 Section 11.4.30 ARM Interrupt Controller (AINTC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 291: Revision Identification Register (Revid)
Table 11-3. Revision Identification Register (REVID) Field Descriptions Field Value Description 31-0 4E82 A900h Revision ID of the AINTC. SPRUH82C – April 2013 – Revised September 2016 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 292: Control Register (Cr)
No nesting Automatic individual nesting (per host interrupt) Automatic global nesting (over all host interrupts) Manual nesting Reserved Reserved ARM Interrupt Controller (AINTC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 293: Global Enable Register (Ger)
The current global nesting level (highest channel that is nested). Writes set the nesting level. In autonesting mode this value is updated internally, unless the auto_override bit is set. SPRUH82C – April 2013 – Revised September 2016 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 294: System Interrupt Status Indexed Set Register (Sisr)
Reserved Reserved INDEX 0-7Fh Writes clear the status of the interrupt given in the INDEX value. Reads return 0. ARM Interrupt Controller (AINTC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 295: System Interrupt Enable Indexed Set Register (Eisr)
Reserved Reserved INDEX 0-7Fh Writes clear the enable of the interrupt given in the INDEX value. Reads return 0. SPRUH82C – April 2013 – Revised September 2016 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 296: Host Interrupt Enable Indexed Set Register (Heisr)
Writes clear the enable of the host interrupt given in the INDEX value. Reads return 0. Writing a 0 clears FIQ. Writing a 1 clears IRQ. ARM Interrupt Controller (AINTC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 297: Vector Base Register (Vbr)
SIZE 0-FFh Size of ISR address spaces. 4 bytes 8 bytes 16 bytes 32 bytes 64 bytes 5h-FFh ... SPRUH82C – April 2013 – Revised September 2016 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 298: Vector Null Register (Vnr)
No Interrupt is pending. Can be used by host to test for a negative value to see if no interrupts are pending. 30-10 Reserved Reserved PRI_INDX 0-3FFh The currently highest priority interrupt index pending across all the host interrupts. ARM Interrupt Controller (AINTC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 299: Global Prioritized Vector Register (Gpvr)
Writing a 0 has no effect. Write a 1 in bit position [n] to set the status of the system interrupt n. SPRUH82C – April 2013 – Revised September 2016 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 300: System Interrupt Status Raw/Set Register 2 (Srsr2)
Writing a 0 has no effect. Write a 1 in bit position [n] to set the status of the system interrupt n + 64. ARM Interrupt Controller (AINTC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 301: System Interrupt Status Raw/Set Register 4 (Srsr4)
Writing a 0 has no effect. Write a 1 in bit position [n] to clear the status of the system interrupt n. SPRUH82C – April 2013 – Revised September 2016 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 302: System Interrupt Status Enabled/Clear Register 2 (Secr2)
Writing a 0 has no effect. Write a 1 in bit position [n] to clear the status of the system interrupt n + 64. ARM Interrupt Controller (AINTC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 303: System Interrupt Status Enabled/Clear Register 4 (Secr4)
Writing a 0 has no effect. Write a 1 in bit position [n] to set the enable for system interrupt n. SPRUH82C – April 2013 – Revised September 2016 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 304: System Interrupt Enable Set Register 2 (Esr2)
Writing a 0 has no effect. Write a 1 in bit position [n] to set the enable for system interrupt n + 64. ARM Interrupt Controller (AINTC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 305: System Interrupt Enable Set Register 4 (Esr4)
Writing a 0 has no effect. Write a 1 in bit position [n] to clear the enable for system interrupt n. SPRUH82C – April 2013 – Revised September 2016 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 306: System Interrupt Enable Clear Register 2 (Ecr2)
Writing a 0 has no effect. Write a 1 in bit position [n] to clear the enable for system interrupt n + 64. ARM Interrupt Controller (AINTC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 307: System Interrupt Enable Clear Register 4 (Ecr4)
Sets the host interrupt for channel N + 1. CHNL_N 0-FFh Sets the channel for the system interrupt N. (N ranges from 0 to 100). SPRUH82C – April 2013 – Revised September 2016 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 308: Host Interrupt Prioritized Index Register 1 (Hipir1)
No Interrupt is pending. 30-10 Reserved Reserved PRI_INDX 0-3FFh Interrupt number of the highest priority pending interrupt for IRQ host interrupt. ARM Interrupt Controller (AINTC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 309: Host Interrupt Nesting Level Register 1 (Hinlr1)
IRQ host interrupt. In auto mode the value is updated internally, unless the OVERRIDE is set and then the write data is used. SPRUH82C – April 2013 – Revised September 2016 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 310: Host Interrupt Enable Register (Hier)
Reserved Enable of IRQ IRQ is disabled. IRQ is enabled. Enable of FIQ FIQ is disabled. FIQ is enabled. ARM Interrupt Controller (AINTC) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 311: Host Interrupt Prioritized Vector Register 1 (Hipvr1)
Value Description 31-0 ADDR 0-FFFF FFFFh The currently highest priority interrupt vector address across for the IRQ host interrupt. SPRUH82C – April 2013 – Revised September 2016 ARM Interrupt Controller (AINTC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 312: Boot Considerations
Chapter 12 SPRUH82C – April 2013 – Revised September 2016 Boot Considerations ........................... Topic Page ..................... 12.1 Introduction Boot Considerations SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 313: Introduction
See Using the AM18xx Bootloader Application Report (SPRABA5) for more details on the ROM Boot Loader, a list of boot pins used, and the complete list of supported boot modes. SPRUH82C – April 2013 – Revised September 2016 Boot Considerations Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 314: Programmable Real-Time Unit Subsystem (Pruss)
PRU Module Interface ....................13.5 Instruction Set ..................13.6 Instruction Formats ..................13.7 PRU Interrupt Controller ......................13.8 Registers Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 315: Overview
External Status 1 (R31) GP / Indexing 1 (R0) Addressability Bit, Byte (8-bit), Halfword (16-bit), Word (32-bit), Pointer SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 316 Accessibility to Internal PRU Structures • Control / Status registers • Debug access to internal registers (R0-R31) and constant table Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 317: Description
RAM/ROM that contains the code that is to be executed. Figure 13-1. PRU Block Diagram SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 318: Constants Table
(ex. c24_blk_index[3:0]) that is programmable through the PRU control register space (0x01C3_7000 - 0x01C3_73FF for PRU0 and 0x01C3_7800 - 0x01C3_7BFF for PRU1). Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 319: Pru Module Interface
"pruX_R30[31:0]" to be used by the program running on the PRU. Each PRU of the PRUSS has a separate mapping to pins, so that there are 64 total general purpose outputs from the PRUSS. SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 320: Instruction Set
Subtracts Rs1 from Op2 then subtracts the saved carry (borrow) With Carry and writes result to Rd and saves carry (borrow). Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 321: Logical Instructions
0xFF if no match) in Rn.b0, and the fields remaining in the scan (including the matching field) in Rn.b1. The Op2 is the field to scan for. SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 322: Program Flow Control Instructions
(un- 1 to infinity masked status bit) is asserted. Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 323: Instruction Formats
7 = Select bits 31:0 from the source register 1 12-8 0-31 = This field selects the register number which contains the first source operand SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 324 7 = Select bits 31:0 of the destination register 0-31 = This field selects the destination register number to which the result should be written. Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 325: Format 1B: (All Arithmetic And Logical Functions - Immediate Op2)
7 = Select bits 31:0 of the destination register 0-31 = This field selects the destination register number to which the result should be written. SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 326: Format 2
7-13 = RESERVED 14 = currently reserved for RFI – Return From Interrupt 15 = SLP – Sleep Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 327: Format 2A: (Jmp,Jal - Register Op2)
0-30 = This field selects the destination register number to which the pre-incremented program counter should be written. Only written for JAL. SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 328: Format 2B: (Jmp, Jal - Immediate Op2)
0-30 = This field selects the destination register number to which the pre-incremented program counter should be written. Only written for JAL. Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 329: Format 2C: (Ldi)
7 = Select bits 31:0 of the destination register 0-31 = This field selects the destination register number to which the result should be written. SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 330: Format 2D: (Lmbd - Leftmost Bit Detect - Register Op2)
6 = Select bits 31:16 from Rd 7 = Select bits 31:0 from Rd 0-31 = Rd register number 0-31 Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 331: Format 2E: (Lmbd - Immediate Op2)
6 = Select bits 31:16 from Rd 7 = Select bits 31:0 from Rd 0-31 = Rd register number 0-31 SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 332: Format 2F: (Scan - Register Op2)
0-31 = Must be identical to Rd RdSel 7 = Select bits 31:0 from Rd 0-31 = Rd register number 0-31 Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 333: Format 2G: (Scan - Immediate Op2)
0 = Do not wake when non-masked status is asserted 1 = Wake when non-masked status is asserted 22-0 RESERVED SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 334: Format 4A: (Quick Arithmetic Test And Branch - Register Op2)
0-255 = This field contains the 8-LSBs of the 2-s complement signed offset for the branch Branch is taken if any of the 3 conditions are satisfied: GT, EQ or LT. Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 335: Format 4B: (Quick Arithmetic Test And Branch - Immediate Op2)
0-255 = This field contains the 8-LSBs of the 2-s complement signed offset for the branch Branch is taken if any of the 3 conditions are satisfied: GT, EQ or LT. SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 336: Format 5A: (Quick Bit Test And Branch - Register Op2)
0-255 = This field contains the 8-LSBs of the 2-s complement signed offset for the branch Branch is taken if any of the 2 conditions are satisfied: BS or BC. Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 337: Format 5B: (Quick Bit Test And Branch - Immediate Op2)
0-255 = This field contains the 8-LSBs of the 2-s complement signed offset for the branch Branch is taken if any of the 2 conditions are satisfied: BS or BC. SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 338: Format 6A: (Lbbo/Sbbo - Register Offset)
0-3 = This field selects the beginning byte number in the source / destination register for the data transfer 0-30 = This field selects the beginning source / destination register number for the data transfer. Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 339: Format 6B: (Lbbo/Sbbo - Immediate Offset)
0-3 = This field selects the beginning byte number in the source / destination register for the data transfer 0-30 = This field selects the beginning source / destination register number for the data transfer. SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 340: Format 6C: (Lbco/Sbco - Register Offset)
0-3 = This field selects the beginning byte number in the source / destination register for the data transfer. 0-30 = This field selects the beginning source / destination register number for the data transfer. Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 341: Pru Interrupt Controller
10 channels inside the INTC (see Figure 1). Interrupts from these 10 channels are further mapped to 10 Host Interrupts. SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 342: Pruss System Events
CFGCHIP3[3]. PRUSSEVTSEL defaults to 0 after reset. Note that not all system events are defined for all devices. Refer to the device datasheet or System Reference Guide for more information. Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 343: Pruss System Events [0:31] Assignments
McBSP0 RX DMA Request McASP0 TX Interrupt or McASP0 RX McASP0 TX Interrupt or McASP0 RX Interrupt Interrupt SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 344: Arm And Dsp Interrupt Controller Mapping
EVTOUT7 Table 13-29. DSP Interrupt Controller Mapping Event Number Source EVTOUT0 EVTOUT1 EVTOUT2 EVTOUT3 EVTOUT4 EVTOUT5 EVTOUT6 EVTOUT7 Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 345: Intc Methodology
2. Enable required host interrupts: By writing to the INDEX field in the host interrupt enable indexed set register (HIEISR), enable the required host interrupts. The host interrupt to enable is the index value SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 346 The system interrupt in position 0 has the highest priority and system interrupt 63 has the lowest priority. So the second level of prioritization picks the lowest position active system interrupt. Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 347 SPIR2) and the System Interrupt Type Registers (SITR1 and SITR2). Polarity of all system interrupts is always high. Type of all system interrupts is always pulse. SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 348: Registers
5. Enable host interrupt by writing index value to HOSTINTENIDX register. 6. Enable interrupt nesting if desired. 7. Globally enable all interrupts through GLBLEN register. 13.8 Registers Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 349: Pruss Memory Map
PRU0 Registers 0x01C37800 0x01C37FFF PRU1 Registers 0x01C38000 0x01C38FFF PRU0 Instruction RAM 0x01C39000 0x01C3BFFF Reserved 0x01C3C000 0x01C3CFFF PRU1 Instruction RAM SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 350: Control Register
Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 351 Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1 on the next cycle after it has been cleared. SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 352: Status Register
Figure 13-27. CYCLECNT Register CYCLECOUNT R/WC-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 353: Stallcnt Register
Figure 13-29. CONTABBLKIDX0 Register RESERVED R/W-0 RESERVED R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 354: Contabproptr0 Register
PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 355: Intgpr0 To Intgpr31 Register
PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 356: Intc Registers
System Interrupt Polarity Register 0 D04h POLARITY1 System Interrupt Polarity Register 1 D80h TYPE0 System Interrupt Type Register 0 Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 357: Revid Register
Table 13-50. GLBLEN Register RESERVED ENABLE R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 358: Glblen Register Field Descriptions
This clears the Raw Status Register bit of the given index. Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 359: Statidxclr Register
This enables the host interrupt output or triggers the output again if already enabled. SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 360: Hstintenidxset Register
Software can write to the Status Set Registers to manually set a system interrupt. There is one bit per system interrupt. Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 361: Statesetint0 Register
Write a 1 in a bit position to clear the status of the system interrupt. Writing a 0 has no effect. SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 362: Statclrint1 Register
Read returns the enable value (0 = disabled, 1 = enabled) Write a 1 in a bit position to set that enable. Writing a 0 has no effect. Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 363: Enableclr0 Register
Sets the channel for the system interrupt N + 1. SYSN_MAP Sets the channel for the system interrupt N. SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 364: Hostmap0 To Hostmap2 Register
Table 13-90. POLARITY0 Register POLARITY R/W-Default_polarity[N] LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 365: Type1 Register
Table 13-96. TYPE1 Register TYPE R/W-Default_type[N] LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH82C – April 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 366: Type1 Register Field Descriptions
31-10 RESERVED ENABLES The enable of the host interrupts (one per bit). 0 = disabled 1 = enabled Programmable Real-Time Unit Subsystem (PRUSS) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 367: Ddr2/Mddr Memory Controller
This chapter describes the DDR2/mobile DDR (mDDR) memory controller..........................Topic Page ..................... 14.1 Introduction ..................... 14.2 Architecture ..................14.3 Supported Use Cases ......................14.4 Registers SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 368: Introduction
• Power-down mode • Prioritized refresh • Programmable refresh rate and backlog counter • Programmable timing parameters • Little-endian mode DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 369: Functional Block Diagram
Furthermore, the on-die terminating resistors of the DDR2/mDDR SDRAM device must be disabled by tying the ODT input pin of the DDR2/mDDR SDRAM to ground. SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 370: Architecture
PLLC1 must be configured to generate a 276-MHz clock on 2X_CLK. Figure 14-2. DDR2/mDDR Memory Controller Clock Block Diagram DDR_CLK DDR_CLK DDR2 memory controller VCLK 2X_CLK PLLC1 PLLC0 DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 371: Signal Descriptions
DDR_CLK DDR_CKE DDR_CS DDR2 DDR_WE memory controller DDR_RAS DDR_CAS DDR_DQM[1:0] DDR_DQS[1:0] DDR_BA[2:0] DDR_A[13:0] DDR_D[15:0] DDR_DQGATE0 DDR_DQGATE1 DDR_VREF 50 Ω DDR_ZP SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 372: Protocol Description(S)
WRT with Inputs the starting column address and begins the write operation. The write operation is followed by a autoprecharge precharge. DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 373: Truth Table For Ddr2/Mddr Sdram Commands
Column Address WRT with Column Address precharge REFR SLFREFR entry SLFREFR exit DESEL Power Down entry Power Down exit SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 374: Refresh Command
REFR command scheduling. Figure 14-4. Refresh Command DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[13:0] DDR_BA[2:0] DDR_DQM[1:0] DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 375: Dcab Command
DCAB command. Figure 14-5. DCAB Command DCAB DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[13:11, 9:0] DDR_A[10] DDR_BA[2:0] DDR_DQM[1:0] SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 376: Deac Command
DEAC command. Figure 14-6. DEAC Command DEAC DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[13:11, 9:0] DDR_A[10] DDR_BA[2:0] DDR_DQM[1:0] DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 377: Actv Command
ACTV command must be issued and a delay of t incurred. Figure 14-7. ACTV Command ACTV DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[13:0] BANK DDR_BA[2:0] DDR_DQM[1:0] SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 378: Ddr2/Mddr Read Command
Figure 14-8. DDR2/mDDR READ Command DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[13:0] DDR_BA[2:0] BANK DDR_A[10] DDR_DQM[1:0] CAS Latency DDR_D[15:0] DDR_DQS[1:0] DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 379: Ddr2/Mddr Wrt Command
DDR_D[15:0] DDR_DQS[1:0] NOTE: This diagrams shows write latency for DDR2. For mDDR, write latency is always equal to 1 cycle. SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 380: Memory Width And Byte Alignment
Description ×16 256 Mbytes Halfword address Figure 14-11. Byte Alignment DDR2 memory controller data bus DDR_D[15:8] DDR_D[7:0] 16-bit memory device DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 381: Address Mapping
2048 (requires 11 row address bits) 4096 (requires 12 row address bits) 8192 (requires 13 row address bits) 16384 (requires 14 row address bits) SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 382: Logical Address-To-Ddr2/Mddr Sdram Address Map For 16-Bit Sdram
DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 383 NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by IBANK) minus 1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1. SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 384: Ddr2/Mddr Sdram Column, Row, And Bank Access
IBANK nbb = 1, 2, or 3 ROWSIZE: nrb = 9, 10, 11, 12, 13, or 14 PAGESIZE: ncb = 8, 9, 10, or 11 DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 385: Address Mapping Diagram (Ibankpos = 1)
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by IBANK) minus 1, and N is number of rows (as determined by ROWSIZE) minus 1. SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 386: Ddr2/Mddr Memory Controller Interface
Write Stores write data coming from on-chip requestors to memory Read Stores read data coming from memory to on-chip requestors DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 387: Ddr2/Mddr Memory Controller Fifo Block Diagram
Selects the highest priority command from pending reads and writes to open rows. If multiple commands have the highest priority, then the DDR2/mDDR memory controller selects the oldest command. SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 388 The EDMA peripheral does not need to implement the above workaround. The above workaround is required for all other peripherals. See your device-specific data manual for more information. DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 389: Refresh Scheduling
T_SXRD + 1 clock cycles before issuing read or write commands. The SDRAM timing register 2 (SDTIMR2) programs the values of T_SXNR and T_SXRD. SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 390: Partial Array Self Refresh For Mobile Ddr
LPMODEN bit, or from clearing the SR_PD bit) until T_CKE + 1 cycles have expired since the power- down command was issued. The value of T_CKE is defined in the SDRAM timing register 2 (SDTIMR2). DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 391: Reset Considerations
Figure 14-16. DDR2/mDDR Memory Controller Reset Block Diagram DDR2/mDDR memory controller Hard registers chip_rst_n Reset from PLLC0 State mod_g_rst_n machine SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 392: Vtp Io Buffer Calibration
DDR2/mDDR memory controller FIFOs will not be lost and the DDR2/mDDR memory controller will ensure read and write commands are completed before starting the initialization sequence. DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 393: Ddr2 Sdram Configuration By Mrs Command
Value of 2 or 3 is programmed based on value of CL bit in SDRAM configuration register (SDCR). DDR_A[3] Burst Type Sequential DDR_A[2:0] Burst Length Value of 8 SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 394: Mobile Ddr Sdram Configuration By Emrs(1) Command
10. Program the SDRAM timing register 1 (SDTIMR1) and SDRAM timing register 2 (SDTIMR2) to the desired values to meet the memory data sheet specification. 11. Clear TIMUNLOCK bit (locked) in SDCR. DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 395: Interrupt Support
The DDR2/mDDR memory controller is a DMA slave peripheral and therefore does not generate DMA events. Data read and write requests may be made directly by masters and by the DMA. SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 396: Power Management
Figure 14-17. DDR2/mDDR Memory Controller Power Sleep Controller Diagram CLKSTOP_REQ VCLKSTOP_REQ CLKSTOP_ACK VCLKSTOP_ACK DDR2/mDDR PLL0_SYSCLK2/2 memory MODCLK VCLK controller MODRST chip_rst_n LRST mod_g_rst_n 2X_CLK PLLC1 DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 397: Emulation Considerations
DDR2/mDDR memory controller before completing VTP IO calibration. See Section 14.2.12 for information on VTP IO calibration. SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 398: Supported Use Cases
DDR_RAS controller DDR_CAS DDR_DQM[0] DDR_DQM[1] DDR_DQS[0] LDQS DDR_DQS[1] UDQS DDR_BA[2:0] BA[2:0] DDR_A[12:0] A[12:0] DDR_D[15:0] DQ[15:0] DDR_ZP 50 Ω DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 399: Sdcr Configuration
To select a CAS latency of 3. IBANK To select 8 internal DDR2 banks. PAGESIZE To select 1024-word page size. SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 400: Ddr2 Memory Refresh Specification
SR_PD Leave a default value. 492h Set to 492h DDR2 clock cycles to meet the DDR2/mDDR memory refresh rate requirement. DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 401: Sdtimr1 Configuration
Read to precharge 15 nS × f ) - 1 DDR2/mDDR_CLK command delay T_CKE CKE minimum pulse width 3 (t cycles) SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 402: Drpyc1R Configuration
Read latency is equal to CAS latency plus round trip board delay for data minus 1 PWRDNEN Programmed to power up the DDR2/mDDR memory controller receivers DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 403: Registers
Table 14-22. Revision ID Register (REVID) Field Descriptions Field Value Description 31-0 4031 1B1Fh Revision ID value of the DDR2/mDDR memory controller. SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 404: Sdram Status Register (Sdrstat)
DLL is not ready, either powered down, in reset, or not locked. DLL is powered up, locked, and ready for operation. Reserved Reserved DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 405: Sdram Configuration Register (Sdcr)
SDRAMEN bit fields may not be changed. DDR2TERM[1:0], MSDRAMEN, DDRDRIVE[1:0], DDR2DDQS, DDR2EN, DDRDLL_DIS, DDREN and SDRAMEN bit fields may be changed. SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 406 2. Write a 0 to the BOOTUNLOCK bit along with the desired value of the SDRAMEN bit. Disable SDRAM Enable SDRAM DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 407 512-word page requiring 9 column address bits. 1024-word page requiring 10 column address bits. 2048-word page requiring 11 column address bits. 4h-7h Reserved SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 408: Sdram Refresh Control Register (Sdrcr)
RR = SDRAM frequency/SDRAM refresh rate where SDRAM refresh rate is derived from the SDRAM data sheet. DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 409: Sdram Timing Register 1 (Sdtimr1)
Corresponds to the t AC timing parameter in the DDR2/mDDR data sheet. Calculate by: T_WTR = (t /DDR_CLK) - 1 SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 410: Sdram Timing Register 2 (Sdtimr2)
Specifies the minimum number of DDR_CLK cycles between transitions on the DDR_CKE pin, minus 1. Corresponds to the t AC timing parameter in the DDR2/mDDR data sheet. Calculate by: T_CKE = t DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 411: Sdram Configuration Register 2 (Sdcr2)
12 row address bits 13 row address bits 14 row address bits 15 row address bits 16 row address bits SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 412: Peripheral Bus Burst Priority Register (Pbbpr)
Recommended setting for typical system operation is between 10h and 20h. 1 memory transfer 2 memory transfers 3 memory transfers 3h-FFh 4 to 256 memory transfers DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 413: Performance Counter 1 Register (Pc1)
32-bit counter that can be configured as specified in the performance counter configuration register (PCC) and the performance counter master region select register (PCMRS). SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 414: Performance Counter Configuration Register (Pcc)
REGION_SEL1 = 7h: PC1 counts accesses to DDR2/mDDR memory controller memory- mapped registers. 13-4 Reserved Any writes to these bit(s) must always have a value of 0. DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 415: Performance Counter Filter Configuration
As the value of this counter approaches 100%, the number of cycles the DDR2/mDDR memory controller has a command in the command FIFO to service approaches 100%. Ah-Fh Reserved SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 416: Performance Counter Master Region Select Register (Pcmrs)
Region select for performance counter 1 register (PC1). PC1 counts total DDR2/mDDR accesses. 1h-6h Reserved PC1 counts total DDR2/mDDR memory controller memory-mapped register accesses. 8h-Fh Reserved DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 417: Ddr Phy Reset Control Register (Drpyrcr)
Always write the default value to these bits. RESET_PHY Reset DDR PHY. No effect. Resets DDR PHY. Reserved 091h Always write the default value to these bits. SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 418: Interrupt Raw Register (Irr)
Illegal memory access type (only set if the LTMSET bit in IMSR is set). See Section 14.2.14 for more details. Reserved Reserved DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 419: Interrupt Mask Set Register (Imsr)
Line trap interrupt is not enabled; a write of 1 to the LTMCLR bit in IMCR occurred. Line trap interrupt is enabled. Reserved Reserved SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 420: Interrupt Mask Clear Register (Imcr)
Line trap interrupt is not enabled. Line trap interrupt is enabled; a write of 1 to the LTMSET bit in IMSR occurred. Reserved Reserved DDR2/mDDR Memory Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 421: Ddr Phy Control Register (Drpyc1R)
CAS latency plus 1. The read latency value is defined in number of MCLK/DDR_CLK cycles. SPRUH82C – April 2013 – Revised September 2016 DDR2/mDDR Memory Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 422: Enhanced Capture (Ecap) Module
This chapter describes the eCAP module..........................Topic Page ..................... 15.1 Introduction ..................... 15.2 Architecture ....................15.3 Applications ......................15.4 Registers Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 423: Introduction
• When not used in capture mode, the ECAP module can be configured as a single channel PWM output SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 424: Architecture
ECAP1INT SyncOut SyncIn ECAP2/ ECAP2 APWM2 GPIO Interrupt module Controller ECAP2INT SyncOut SyncIn ECAPx/ ECAPx APWMx module ECAPxINT SyncOut Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 425: Capture And Apwm Operating Mode
(2) In APWM mode, writing any value to CAP1/CAP2 active registers also writes the same value to the corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the shadow registers CAP3/CAP4 invokes the shadow mode. SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 426: Capture Mode Description
Oneshot Controller CTR_OVF Capture Control Flag CTR=PRD control CTR=CMP ECCTL2 [ RE-ARM, CONT/ONESHT, STOP_WRAP] Registers: ECEINT, ECFLG, ECCLR, ECFRC Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 427: Event Prescale Control
Figure 15-5. Prescale Function Waveforms ECAPx PSout div 2 PSout div 4 PSout div 6 PSout div 8 PSout div 10 SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 428: Continuous/One-Shot Block Diagram
2:4 MUX CEVT1 CEVT2 Modulo 4 CEVT3 Stop counter CEVT4 Mod_eq One−shot control logic Stop value (2b) ECCTL2[STOP_WRAP] ECCTL2[RE−ARM] ECCTL2[CONT/ONESHT] Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 429: Counter And Synchronization Block Diagram
ECCTL2[SYNCOSEL] SYNCI CTR=PRD Disable SYNCO Disable ECCTL2[SYNCI_EN] Sync out select CTRPHS LD_CTRPHS Delta−mode TSCTR (counter 32b) SYSCLK CTR−OVF CTR[31−0] SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 430 (ECCTL2[CAP/APWM == 0]). The CTR = PRD, CTR = CMP flags are only valid in APWM mode (ECCTL2[CAP/APWM == 1]). CNTOVF flag is valid in both modes. Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 431: Interrupts In Ecap Module
ECCLR ECFRC Latch CTROVF ECEINT ECFLG Clear ECCLR ECFRC Latch ECEINT PRDEQ ECFLG Clear ECCLR ECFRC Latch ECEINT CMPEQ SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 432: Pwm Waveform Details Of Apwm Mode Operation
CMP = PERIOD, output low except for 1 cycle (<100% duty) CMP = PERIOD+1, output low for complete period (100% duty) Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 433: Applications
#define EC_CAP_MODE #define EC_APWM_MODE // APWMPOL bit #define EC_ACTV_HI #define EC_ACTV_LO // Generic #define EC_DISABLE #define EC_ENABLE #define EC_FORCE SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 434: Absolute Time-Stamp Operation Rising Edge Trigger Example
CAP1 CAP2 CAP3 CAP4 All capture values valid Polarity selection (can be read) at this time Capture registers [1−4] Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 435: Ecap Initialization For Cap Mode Absolute Time, Rising Edge Trigger
Period1 = TSt2-TSt1; // Calculate 1st period Period2 = TSt3-TSt2; // Calculate 2nd period Period3 = TSt4-TSt3; // Calculate 3rd period SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 436: Absolute Time-Stamp Operation Rising And Falling Edge Trigger Example
CEVT3 CEVT1 CEVT3 CEVT1 CAPx pin FFFFFFFF CTR[0−31] 00000000 MOD4 CAP1 CAP2 CAP3 CAP4 Polarity selection Capture registers [1−4] Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 437: Ecap Initialization For Cap Mode Absolute Time, Rising And Falling Edge Trigger
Period1 = TSt3-TSt1; // Calculate 1st period DutyOnTime1 = TSt2-TSt1; // Calculate On time DutyOffTime1 = TSt3-TSt2; // Calculate Off time SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 438: Time Difference (Delta) Operation Rising Edge Trigger Example
CTR value at CEVT1 CAP2 CAP3 CAP4 Polarity selection Capture registers [1−4] All capture values valid (can be read) at this time Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 439: Ecap Initialization For Cap Mode Delta Time, Rising Edge Trigger
// Fetch Time-Stamp captured at T2 Period2 = ECAPxRegs.CAP3; // Fetch Time-Stamp captured at T3 Period3 = ECAPxRegs.CAP4; // Fetch Time-Stamp captured at T4 SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 440: Time Difference (Delta) Operation Rising And Falling Edge Trigger Example
CAPx pin FFFFFFFF CTR[0−31] 00000000 MOD4 CAP1 CTR value at CEVT1 CAP2 CAP3 CAP4 Polarity selection Capture registers [1−4] Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 441: Ecap Initialization For Cap Mode Delta Time, Rising And Falling Edge Triggers
DutyOffTime2 = ECAPxRegs.CAP1; // Fetch Time-Stamp captured at T1 Period1 = DutyOnTime1 + DutyOffTime1; Period2 = DutyOnTime2 + DutyOffTime2; SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 442: Application Of The Apwm Mode
Figure 15-14. PWM Waveform Details of APWM Mode Operation TSCTR FFFFFFFF 1000h APRD 500h ACMP 300h 0000000C APWMx (o/p pin) Off−time Period time Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 443: Ecap Initialization For Apwm Mode
Freq = 5 × F1. Note here values are in decimal notation. Also, only the APWM1 output waveform is shown. SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 444: Multichannel Pwm Example Using 4 Ecap Modules
APWM1 (o/p pin) CTR=PRD (SyncOut) Time Phase = 0° Slave APWM(2−4) module/s 10,000 APRD(2) 5,000 APRD(3) 4,000 APRD(4) Time Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 445: Ecap1 Initialization For Multichannel Pwm Generation With Synchronization
CAP1 4000 CTRPHS CTRPHS ECCTL2 CAP_APWM EC_APWM_MODE ECCTL2 APWMPOL EC_ACTV_HI ECCTL2 SYNCI_EN EC_ENABLE ECCTL2 SYNCO_SEL EC_SYNCO_DIS ECCTL2 TSCTRSTOP EC_RUN SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 446 (Legs). Note eCAP1 module is the Master and issues a sync out pulse to the slaves (modules 2, 3) whenever TSCTR = Period value. Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 447: Multiphase (Channel) Interleaved Pwm Example Using 3 Ecap Modules
APWM1 APWM2 APWM3 Vout TSCTR 1200 APRD(1) APRD(1) SYNCO pulse (CTR=PRD) APWM1 Φ2=120° CTRPHS(2)=800 APWM2 Φ3=240° CTRPHS(3)=400 APWM3 SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 448: Ecap1 Initialization For Multichannel Pwm Generation With Phase Control
// Set Duty cycle i.e. compare value = 700 ECAP3Regs.CAP2 = 700; // Set Duty cycle i.e. compare value = 700 Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 449: Registers
Table 15-14. Time-Stamp Counter Register (TSCTR) Field Descriptions Field Value Description 31-0 TSCTR 0-FFFF FFFFh Active 32-bit counter register that is used as the capture time-base SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 450: Counter Phase Control Register (Ctrphs)
• Time-Stamp (i.e., counter value) during a capture event • Software - may be useful for test purposes • APRD active register when used in APWM mode Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 451: Capture 2 Register (Cap2)
In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow (APRD) register. You update the PWM period value through this register. In this mode, CAP3 shadows CAP1. SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 452: Capture 4 Register (Cap4)
Enable Loading of CAP1-4 registers on a capture event Disable CAP1-4 register loads at capture event time. Enable CAP1-4 register loads at capture event time. Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 453 Capture Event 1 Polarity select Capture Event 1 triggered on a rising edge (RE) Capture Event 1 triggered on a falling edge (FE) SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 454: Ecap Control Register 2 (Ecctl2)
Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event. TSCTRSTOP Time Stamp (TSCTR) Counter Stop (freeze) Control TSCTR stopped TSCTR free-running Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 455: Ecap Interrupt Enable Register (Eceint)
4. Configure peripheral registers 5. Clear spurious eCAP interrupt flags 6. Enable eCAP interrupts 7. Start eCAP counter 8. Enable global interrupts SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 456: Ecap Interrupt Enable Register (Eceint)
Capture Event 1 Interrupt Enable Disable Capture Event 1 as an Interrupt source Enable Capture Event 1 as an Interrupt source Reserved Reserved Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 457: Ecap Interrupt Flag Register (Ecflg)
Indicates the first event occurred at ECAPn pin. Global Interrupt Status Flag Indicates no interrupt generated. Indicates that an interrupt was generated. SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 458: Ecap Interrupt Clear Register (Ecclr)
Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1. Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 459: Ecap Interrupt Forcing Register (Ecfrc)
Force Capture Event 1 No effect. Always reads back a 0. Writing a 1 sets the CEVT1 flag bit. Reserved Reserved SPRUH82C – April 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 460: Revision Id Register (Revid)
LEGEND: R = Read only; -n = value after reset Table 15-26. Revision ID Register (REVID) Field Descriptions Field Value Description 31-0 44D2 2100h Revision ID. Enhanced Capture (eCAP) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 461: Enhanced High-Resolution Pulse-Width Modulator (Ehrpwm)
........................... Topic Page ..................... 16.1 Introduction ..................... 16.2 Architecture ..............16.3 Applications to Power Topologies ......................16.4 Registers SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 462: Introduction
Each ePWM module consists of seven submodules and is connected within a system via the signals shown in Figure 16-2. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 463: Multiple Epwm Modules
EPWM2A Interrupt GPIO ePWM2 module EPWM2B Controller SYNCO SYNCI EPWMxINT EPWMxA ePWMx module EPWMxB SYNCO Peripheral Frame 1 SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 464: Submodules And Signal Connections For An Epwm Module
Figure 16-3 also shows the key internal submodule interconnect signals. Each submodule is described in detail in Section 16.2. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 465: Epwm Submodules And Critical Internal Signal Interconnects
(DB) (PC) (TZ) EPWMB EPWMxB CMPB active (16) EPWMxTZINT CMPB shadow (16) CTR = 0 TZ1 to TZn SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 466: Register Mapping
These registers are only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these locations are reserved. See your device-specific data manual to determine which instances include the HRPWM. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 467: Architecture
• Duty cycle of the second and subsequent pulses. • Bypass the PWM-chopper module entirely. In this case the PWM waveform is passed through without modification. SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 468 Section 16.2.10 • Enable extended time resolution capabilities (HRPWM) • Configure finer time granularity control or edge positioning Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 469 // = = = = = = = = = = = = = = = = = = = = = = = = = = // CHPEN bit #define CHP_DISABLE #define CHP_ENABLE SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 470: Proper Interrupt Initialization Procedure
3. Initialize peripheral registers 4. Clear any spurious ePWM flags 5. Enable ePWM interrupts 6. Enable global interrupts Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 471: Time-Base (Tb) Submodule
Configure the rate of the time-base clock; a prescaled version of the CPU system clock (SYSCLKOUT). This allows the time-base counter to increment/decrement at a slower rate. SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 472: Time-Base Submodule Signals And Registers
TBCTL[PHSEN] TBCNT Select Counter Active Reg Disable TBPHS TBCTL[SYNCOSEL] Phase Active Reg Clock SYSCLKOUT TBCLK Prescale TBCTL[HSPCLKDIV] TBCTL[CLKDIV] Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 473: Key Time-Base Signals
When it reaches zero, the time-base counter is reset to the period value and it begins to decrement once again. SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 474: Time-Base Frequency And Period
TBPRD memory address goes directly to the active register. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 475: Time-Base Counter Synchronization Scheme 1
Figure 16-7. Time-Base Counter Synchronization Scheme 1 GPIO MUX EPWM1SYNCI ePWM1 EPWM1SYNCO EPWM2SYNCI ePWM2 EPWM2SYNCO EPWM3SYNCI ePWM3 EPWM3SYNCO EPWMxSYNCI ePWMx EPWMxSYNCO SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 476 Figure 16-8 Figure 16-11 show when events are generated and how the time-base responds to an EPWMxSYNCI signal. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 477: Time-Base Up-Count Mode Waveforms
Figure 16-8. Time-Base Up-Count Mode Waveforms TBCNT FFFFh TBPRD (value) TBPHS (value) 0000h EPWMxSYNCI CTR_dir CTR = 0 CTR = PRD CNT_max SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 478: Time-Base Down-Count Mode Waveforms
FFFFh TBPRD (value) TBPHS (value) 0000h EPWMxSYNCI CTR_dir DOWN DOWN DOWN CTR = 0 CTR = PRD CNT_max Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 479: Time-Base Up-Down Count Waveforms, Tbctl[Phsdir = 1] Count Up On Synchronization Event
FFFFh TBPRD (value) TBPHS (value) 0000h EPWMxSYNCI CTR_dir DOWN DOWN DOWN CTR = 0 CTR = PRD CNT_max SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 480: Counter-Compare (Cc) Submodule
CTR = PRD CMPCTL[SHDWBFULL] load Compare B Active Reg. CTR = 0 CMPB CMPCTL[SHDWBMODE] Compare B Shadow Reg. CMPCTL[LOADBMODE] Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 481: Counter-Compare Submodule Registers
Time-base counter equal to zero. TBCNT = 0000h Used to load active counter-compare A and B registers from the shadow register SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 482 To best illustrate the operation of the first three modes, the timing diagrams in Figure 16-14 Figure 16- show when events are generated and how the EPWMxSYNCI signal interacts. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 483: Counter-Compare Event Waveforms In Up-Count Mode
TBCNT FFFFh TBPRD (value) CMPA (value) CMPB (value) TBPHS (value) 0000h EPWMxSYNCI CTR = CMPA CTR = CMPB SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 484: Counter-Compare Events In Up-Down-Count Mode, Tbctl[Phsdir = 0] Count Down On Synchronization Event
TBCNT FFFFh TBPRD (value) CMPA (value) CMPB (value) TBPHS (value) 0000h EPWMxSYNCI CTR = CMPB CTR = CMPA Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 485: Action-Qualifier (Aq) Submodule
AQCTLB Action-Qualifier Control Register For Output B (EPWMxB) AQSFRC Action-Qualifier Software Force Register AQCSFRC Action-Qualifier Continuous Software Force SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 486: Action-Qualifier Submodule Inputs And Outputs
Nothing" option prevents an event from causing an action on the EPWMxA and EPWMxB outputs, this event can still trigger interrupts. See the event-trigger submodule description in Section 16.2.9 details. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 487: Possible Action-Qualifier Actions For Epwmxa And Epwmxb Outputs
Figure 16-20. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs TB Counter equals: Actions force Comp Comp Zero Period Do Nothing Clear Low Set High Toggle SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 488: Action-Qualifier Event Priority For Up-Down-Count Mode
Counter equal to CMPB on down-count (CBD) Counter equal to CMPA on down-count (CAD) 5 (Lowest) Counter equal to period (TBPRD) Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 489: Behavior If Cmpa/Cmpb Is Greater Than The Period
PWM. Modulate the compare value from 0 to TBPRD+1 to achieve 0-100% PWM duty. SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 490: Up-Down-Count Mode Symmetrical Waveform
CMPA = 2, 50% Duty Case 3: EPWMxA/EPWMxB CMPA = 1, 75% Duty Case 4: EPWMxA/EPWMxB CMPA = 0, 100% Duty Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 491: Up, Single Edge Asymmetric Waveform, With Independent Modulation On Epwmxa And Epwmxb-Active High
(5) Actions at zero and period, although appearing to occur concurrently, are actually separated by one TBCLK period. TBCNT wraps from period to 0000h. SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 492: Epwmx Initialization For
Value Comments CMPA CMPA Duty1A Adjust duty for output EPWM1A CMPB CMPB Duty1B Adjust duty for output EPWM1B Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 493: Up, Single Edge Asymmetric Waveform With Independent Modulation On Epwmxa And Epwmxb-Active Low
(5) Actions at zero and period, although appearing to occur concurrently, are actually separated by one TBCLK period. TBCNT wraps from period to 0000h. SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 494: Epwmx Initialization For
Value Comments CMPA CMPA Duty1A Adjust duty for output EPWM1A CMPB CMPB Duty1B Adjust duty for output EPWM1B Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 495: Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation On Epwmxa
(4) EPWMxB can be used to generate a 50% duty square wave with frequency = 1/2 × ((TBPRD + 1) × TBCLK) SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 496: Epwmx Initialization For
Table 16-18. EPWMx Run Time Changes for Figure 16-24 Register Value Comments CMPA CMPA EdgePosA Adjust duty for output EPWM1A CMPB CMPB EdgePosB Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 497: Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation On Epwmxa And Epwmxb - Active Low
(3) Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to CMPB). (4) Outputs EPWMxA and EPWMxB can drive independent power switches SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 498: Epwmx Initialization For
Value Comments CMPA CMPA Duty1A Adjust duty for output EPWM1A CMPB CMPB Duty1B Adjust duty for output EPWM1B Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 499: Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation On Epwmxa And Epwmxb - Complementary
(5) Dead-band = CMPB - CMPA (fully programmable edge placement by software). Note the dead-band module is also available if the more classical edge delay method is required. SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 500: Epwmx Initialization For
Value Comments CMPA CMPA Duty1A Adjust duty for output EPWM1A CMPB CMPB Duty1B Adjust duty for output EPWM1B Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 501: Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation On Epwmxa-Active Low
(5) To change this example to active high, CMPA and CMPB actions need to be inverted (i.e., Set ! Clear and Clear Set). (6) Duty modulation for EPWMxB is fixed at 50% (utilizes spare action resources for EPWMxB) SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 502: Epwmx Initialization For
Table 16-24. EPWMx Run Time Changes for Figure 16-27 Register Value Comments CMPA CMPA EdgePosA Adjust duty for output EPWM1A CMPB CMPB EdgePosB Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 503: Dead-Band Generator (Db) Submodule
DBCTL Dead-Band Control Register DBRED Dead-Band Rising Edge Delay Count Register DBFED Dead-Band Falling Edge Delay Count Register SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 504: Configuration Options For The Dead-Band Generator Submodule
EPWMxA in (10-bit counter) Falling edge 0 S3 delay EPWMxB (10-bit counter) DBCTL[IN_MODE] DBCTL[POLSEL] DBCTL[OUT_MODE] EPWMxB in Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 505: Classical Dead-Band Operating Modes
These are classical dead-band modes and assume that DBCTL[IN_MODE] = 0,0. That is, EPWMxA in is the source for both the falling-edge and rising-edge delays. Enhanced, non-traditional modes can be achieved by changing the IN_MODE configuration. SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 506: Dead-Band Waveforms For Typical Cases (0% < Duty < 100%)
RED = DBRED × T TBCLK Where T is the period of TBCLK, the prescaled version of SYSCLKOUT. TBCLK Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 507: Pwm-Chopper (Pc) Submodule
The PWM-chopper submodule operation is controlled via the register in Table 16-27. Table 16-27. PWM-Chopper Submodule Registers Acronym Register Description Address Offset Shadowed PCCTL PWM-chopper Control Register SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 508: Pwm-Chopper Submodule Signals And Registers
Divider and PSCLK [CHPEN] duty control PCCTL [OSHTWTH] PCCTL[CHPFREQ] PCCTL[CHPDUTY] Pulse-width PWMB_ch EPWMxB shot OSHT EPWMxA Start Bypass Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 509: Simple Pwm-Chopper Submodule Waveforms Showing Chopping Action Only
Subsequent Sustaining Pulses Start OSHT pulse EPWMxA in PSCLK Prog. pulse width (OSHTWTH) OSHT EPWMxA out Sustaining pulses SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 510: Pwm-Chopper Submodule Waveforms Showing The Pulse Width (Duty Cycle) Control Of Sustaining Pulses
Sustaining Pulses PSCLK PSCLK period PSCLK Period 62.5% 87.5% 37.5% 12.5% Duty Duty Duty Duty Duty Duty Duty Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 511: Trip-Zone (Tz) Submodule
Software-forced tripping is also supported. • The trip-zone submodule can be fully bypassed if it is not required. SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 512: Trip-Zone Submodule Registers
TZCTL[TZA] and TZCTL[TZB] register bits. One of four possible actions, shown in Table 16-29, can be taken on a trip event. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 513: Possible Actions On A Trip Event
16.2.8.4 Generating Trip Event Interrupts Figure 16-37 Figure 16-38 illustrate the trip-zone submodule control and interrupt logic, respectively. SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 514: Trip-Zone Submodule Mode Control Logic
TZEINT[CBC] TZFLG[OST] Generate EPWMxTZINT interrupt Clear TZCLR[OST] (Interrupt controller) pulse when input=1 Latch OSHT trip event TZEINT[OST] Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 515: Event-Trigger (Et) Submodule
Event-Trigger Selection Register ETPS Event-Trigger Prescale Register ETFLG Event-Trigger Flag Register ETCLR Event-Trigger Clear Register ETFRC Event-Trigger Force Register SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 516: Event-Trigger Submodule Inter-Connectivity To Interrupt Controller
ETPS reg CTRU=CMPB qualifier count CTR = CMPB CTRD=CMPB ETFLG reg clear ETCLR reg CTR_dir count ETFRC reg Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 517 INTCNT. The counter will behave as described above when INTCNT = INTPRD. When INTPRD = 0, the counter is disabled and hence no events will be detected and the ETFRC[INT] bit is also ignored. SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 518: Event-Trigger Interrupt Generator
EPWMxINT 2-bit when ETFRC[INT] Counter input = 1 CTR=0 CTR=PRD Inc CNT CTRU=CMPA CTRD=CMPA ETSEL[INT] CTRU=CMPB CTRD=CMPB ETPS[INTPRD] Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 519: High-Resolution Pwm (Hrpwm) Submodule
(DB) (PC) (TZ) EPWMB EPWMxB CMPB active (16) EPWMxTZINT CMPB shadow (16) TZ1 to TZn CTR = 0 SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 520: Resolution Calculations For Conventionally Generated Pwm
Single-phase buck, boost, and flyback • Multi-phase buck, boost, and flyback • Phase-shifted full bridge • Direct modulation of D-Class power amplifiers Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 521: Operating Logic Using Mep
Shadowed TBPHSHR Extension Register for HRPWM Phase CMPAHR Extension Register for HRPWM Duty HRCNFG HRPWM Configuration Register 1040h SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 522: Relationship Between Mep Steps, Pwm Frequency And Resolution
PWM minimum frequency is based on a maximum period value, TBPRD = 65 535. PWM mode is asymmetrical up-count. Resolution in bits is given for the maximum PWM frequency stated. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 523: Required Pwm Waveform For A Requested Duty
For a PWM Period register value of 80 counts, PWM Period = 80 × 10 ns = 800 ns, PWM frequency = 1/800 ns = 1.25 MHz Assumed MEP step size for the above example = 180 ps SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 524 = 1600h + 180h CMPAHR value = 1780h; CMPAHR value = 1700h, lower 8 bits will be ignored by hardware. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 525: Low % Duty Cycle Range Limitation Example When Pwm Frequency = 1 Mhz
16-48. In this case low percent duty limitation is no longer an issue. Figure 16-48. High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz EPWM1A SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 526: Applications To Power Topologies
Figure 16-49. Simplified ePWM Module SyncIn Phase reg EPWMxA Φ=0° EPWMxB CTR = 0 CTR=CMPB SyncOut Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 527: Key Configuration Capabilities
Phase reg SyncIn SyncIn Phase reg Φ=0° EPWM2A Φ=0° EPWM1A EPWM1B EPWM2B CTR=0 CTR=0 CTR=CMPB CTR=CMPB SyncOut SyncOut SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 528: Controlling Multiple Buck Converters With Independent Frequencies
EPWM4B CTR=0 EPWM4A CTR=CMPB SyncOut NOTE: Θ = X indicates value in phase register is a "don't care" Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 529: Buck Waveforms For (Note: Only Three Bucks Shown Here)
Figure 16-51 (Note: Only three bucks shown here) 1200 EPWM1A 1400 EPWM2A EPWM3A Indicates this event triggers an interrupt SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 530: Epwm1 Initialization For
CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR = 0 LOADBMODE CC_CTR_ZERO Load on CTR = 0 AQCTLA AQ_CLEAR AQ_SET Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 531: Controlling Multiple Buck Converters With Same Frequencies
Buck #3 Slave Phase reg EPWM2A SyncIn Φ=X EPWM2A EPWM2B Vin4 Vout4 CTR=0 CTR=CMPB Buck #4 SyncOut EPWM2B SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 532: Pwm2 Pwm1
Applications to Power Topologies www.ti.com Figure 16-54. Buck Waveforms for Figure 16-53 (Note: F PWM2 PWM1 EPWM1A EPWM1B EPWM2A EPWM2B Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 533: Epwm1 Initialization For
EPwm2Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM2A EPwm2Regs.CMPB = 300; // adjust duty for output EPWM2B SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 534: Controlling Multiple Half H-Bridge (Hhb) Converters
CTR=0 CTR=CMPB EPWM1B SyncOut Slave Phase reg SyncIn DC_bus EPWM2A out2 Φ=0° EPWM2B CTR=0 EPWM2A CTR=CMPB SyncOut EPWM2B Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 535: Pwm2 Pwm1
Figure 16-56. Half-H Bridge Waveforms for Figure 16-55 (Note: F PWM2 PWM1 EPWM1A EPWM1B Pulse Center EPWM2A EPWM2B Pulse Center SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 536: Epwm1 Initialization For
EPwm2Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM2A EPwm2Regs.CMPB = 250; // adjust duty for output EPWM2B Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 537: Controlling Dual 3-Phase Inverters For Motors (Aci And Pmsm)
3 phase motor SyncOut Slave Phase reg SyncIn 3 phase inverter #2 Φ=0° EPWM6A EPWM6B CTR=0 CTR=CMPB SyncOut SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 538: 3-Phase Inverter Waveforms For (Only One Inverter Shown)
Figure 16-58. 3-Phase Inverter Waveforms for Figure 16-57 (Only One Inverter Shown) EPWM1A EPWM1B Φ2=0 EPWM2A EPWM2B Φ3=0 EPWM3A EPWM3B Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 539: Epwm1 Initialization For
Enable Dead-band module POLSEL DB_ACTV_HIC Active Hi complementary DBFED DBFED FED = 50 TBCLKs DBRED RED = 50 TBCLKs SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 540: Epwm3 Initialization For
EPwm2Regs.CMPA.half.CMPA = 600; // adjust duty for output EPWM2A EPwm3Regs.CMPA.half.CMPA = 700; // adjust duty for output EPWM3A Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 541: Practical Applications Using Phase Control Between Pwm Modules
SyncIn pulse (CTR = PRD), the value of TBPHS = 200 is loaded into the slave TBCNT register so the slave time-base is always leading the master's time-base by 120°. SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 542: Controlling A 3-Phase Interleaved Dc/Dc Converter
TBPHS(3,3) = (600/3) × (3 - 1) = 200 × 2 = 400 (Phase value for Slave module 3) Figure 16-62 shows the waveforms for the configuration in Figure 16-61. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 543: Control Of A 3-Phase Interleaved Dc/Dc Converter
SyncIn EPWM2A Φ=120° Φ=120° EPWM2B CTR=0 CTR=CMPB SyncOut Slave Phase reg SyncIn EPWM3A Φ=240° EPWM3B CTR=0 CTR=CMPB SyncOut SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 544: 3-Phase Interleaved Dc/Dc Converter Waveforms For
Figure 16-62. 3-Phase Interleaved DC/DC Converter Waveforms for Figure 16-61 EPWM1A EPWM1B Φ2=120° TBPHS (=300) EPWM2A EPWM2B Φ2=120° TBPHS (=300) EPWM3A EPWM3B Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 545: Epwm1 Initialization For
Enable Dead-band module POLSEL DB_ACTV_HIC Active Hi complementary DBFED DBFED FED = 20 TBCLKs DBRED RED = 20 TBCLKs SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 546: Epwm3 Initialization For
EPwm2Regs.CMPA.half.CMPA = 285; // adjust duty for output EPWM2A EPwm3Regs.CMPA.half.CMPA = 285; // adjust duty for output EPWM3A Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 547: Controlling Zero Voltage Switched Full Bridge (Zvsfb) Converter
EPWM1A EPWM2A SyncOut Slave Phase reg SyncIn EPWM2A Φ=Var° EPWM1B EPWM2B EPWM2B CTR=0 CTR=CMPB SyncOut Var = Variable SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 548: Zvs Full-H Bridge Waveforms
Figure 16-64. ZVS Full-H Bridge Waveforms 1200 EPWM1A ZVS transition Power phase EPWM1B ZVS transition Φ2=variable TBPHS =(1200−Φ2) EPWM2A EPWM2B Power phase Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 549: Epwm1 Initialization For
// Update ZVS transition interval EPwm2Regs.DBFED = FED2_NewValue; // Update ZVS transition interval EPwm2Regs.DBRED = RED2_NewValue; // Update ZVS transition interval SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 550: Registers
R/W-0 R/W-0 R/W-0 R/W-0 R/W-3h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 551: Time-Base Control Register (Tbctl) Field Descriptions
CTR = 0: Time-base counter equal to zero (TBCNT = 0000h) CTR = CMPB : Time-base counter equal to counter-compare B (TBCNT = CMPB) Disable EPWMxSYNCO signal SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 552: Time-Base Status Register (Tbsts)
16.4.1.3 Time-Base Phase Register (TBPHS) The time-base phase register (TBPHS) is shown in Figure 16-67 and described in Table 16-54. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 553: Time-Base Phase Register (Tbphs)
Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs; the write is NOT synchronized to the time-base clock (TBCLK) and the register is not shadowed. SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 554: Counter-Compare Submodule Registers
This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, this location is reserved. See your device-specific data manual to determine which instances include the HRPWM. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 555: Counter-Compare Control Register (Cmpctl)
Load on CTR = PRD: Time-base counter equal to period (TBCNT = TBPRD) Load on either CTR = 0 or CTR = PRD Freeze (no loads possible) SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 556: Counter-Compare A Register (Cmpa)
• In either mode, the active and shadow registers share the same memory map address. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 557: Action-Qualifier Submodule Registers
Action-Qualifier Output B Control Register Section 16.4.3.2 AQSFRC Action-Qualifier Software Force Register Section 16.4.3.3 AQCSFRC Action-Qualifier Continuous Software Force Register Section 16.4.3.4 SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 558: Action-Qualifier Output A Control Register (Aqctla)
Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 559: Action-Qualifier Output B Control Register (Aqctlb)
Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low. SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 560: Action-Qualifier Software Force Register (Aqsfrc)
Set (high) Toggle (Low → High, High → Low) Note: This action is not qualified by counter direction (CNT_dir) Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 561: Dead-Band Generator Submodule Registers
DBRED Dead-Band Generator Rising Edge Delay Register Section 16.4.4.2 DBFED Dead-Band Generator Falling Edge Delay Register Section 16.4.4.3 SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 562: Dead-Band Generator Control Register (Dbctl)
Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB. The input signal for the delay is determined by DBCTL[IN_MODE]. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 563: Dead-Band Generator Rising Edge Delay Register (Dbred)
Table 16-69. Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions Bits Name Value Description 15-10 Reserved Reserved 0-3FFh Falling Edge Delay Count. 10-bit counter SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 564: Pwm-Chopper Submodule Register
4 × SYSCLKOUT/8 wide to 16 × SYSCLKOUT/8 wide CHPEN PWM-chopping Enable Disable (bypass) PWM chopping function Enable chopping function Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 565: Trip-Zone Submodule Registers
Disable TZn as a CBC trip source for this ePWM module. Enable TZn as a CBC trip source for this ePWM module. SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 566: Trip-Zone Control Register (Tzctl)
Disable cycle-by-cycle interrupt generation. Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMxTZINT interrupt. Reserved Reserved Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 567: Trip-Zone Flag Register (Tzflg)
This bit is cleared by writing the appropriate value to the TZCLR register (Section 16.4.6.5). SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 568: Trip-Zone Clear Register (Tzclr)
Writing of 0 is ignored. Always reads back a 0. Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit. Reserved Reserved Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 569: Event-Trigger Submodule Registers
Enable event: time-base counter equal to CMPB when the timer is incrementing. Enable event: time-base counter equal to CMPB when the timer is decrementing. SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 570: Event-Trigger Prescale Register (Etps)
Generate an interrupt on the first event INTCNT = 01 (first event) Generate interrupt on ETPS[INTCNT] = 1,0 (second event) Generate interrupt on ETPS[INTCNT] = 1,1 (third event) Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 571: Event-Trigger Flag Register (Etflg)
Writing a 0 has no effect. Always reads back a 0. Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated. SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 572: High-Resolution Pwm Submodule Registers
Time-Base Phase High-Resolution Register Section 16.4.8.1 CMPAHR Counter-Compare A High-Resolution Register Section 16.4.8.2 1040h HRCNFG HRPWM Configuration Register Section 16.4.8.3 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 573: Time-Base Phase High-Resolution Register (Tbphshr)
Compare A High-Resolution register bits for MEP step control. A minimum value of 1h is needed to enable HRPWM capabilities. Valid MEP range of operation 1-255h. Reserved Reserved SPRUH82C – April 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 574: Hrpwm Configuration Register (Hrcnfg)
HRPWM capability is disabled (default on reset) MEP control of rising edge MEP control of falling edge MEP control of both edges Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 575: Enhanced Direct Memory Access (Edma3) Controller
Architecture .................... 17.3 Transfer Examples ......................17.4 Registers ........................ 17.5 Tips ..................17.6 Setting Up a Transfer SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 576: Introduction
Debug visibility – Queue watermarking – Error and status recording to facilitate debug – Missed event detection Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 577 – 1 transfer controller (EDMA3_1_TC0) – 5 interrupts: • EDMA3_1_CC0_INT0 • EDMA3_1_CC0_INT1 • EDMA3_1_CC0_INT2 • EDMA3_1_CC0_INT3 • EDMA3_1_CC0_ERRINT SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 578 Configuration (SYSCFG) Module chapter for details to change the default burst size value. – Error interrupt: EDMA3_1_TC0_ERRINT – EDMA3 channel controller used: EDMA3_1_CC0 Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 579: Functional Block Diagram
A dummy set results in the EDMA3CC performing a dummy transfer. This is not an error condition. A null set results in an error condition. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 580 QDMA channel n mapping register (QCHMAPn) and can point to any PaRAM set entry. TR synchronization See Trigger event. (sync) event Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 581: Architecture
DMA channels being higher priority than the QDMA channels. Among the two groups of channels, the lowest-numbered channel is the highest priority. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 582: Edma3 Channel Controller (Edma3Cc) Block Diagram
(like missed events, exceeding event queue thresholds, etc.). For more details on error interrupts, see Section 17.2.9.4. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 583: Edma3 Transfer Controller (Edma3Tc) Block Diagram
For details on command fragmentation and optimization, see Section 17.2.11.1.2. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 584: Types Of Edma3 Transfers
CCNT frames in Block/3rd dimmension Frame CCNT Array 1 Array 2 Array BCNT BCNT arrays in Frame/2nd dimmension Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 585: A-Synchronized Transfers (Acnt = N, Bcnt = 4, Ccnt = 3)
CIDX (SRC|DST) (SRC|DST) (SRC|DST) BIDX BIDX BIDX Frame 2 Array 0 Array 1 Array 2 Array 3 SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 586: Ab-Synchronized Transfers (Acnt = N, Bcnt = 4, Ccnt = 3)
NOTE: ABC-synchronized transfers are not directly supported. But can be logically achieved by chaining between multiple AB-synchronized transfers. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 587: Parameter Ram (Param)
Parameter set n Note: n is the number of PaRAM sets supported in the EDMA3CC for a specific device. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 588: Edma3 Channel Parameter Description
32-bit accesses on the parameter RAM for best code compatibility. For example, switching the endianness of the processor swaps addresses of the 16-bit fields, but 32-bit accesses avoid the issue entirely. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 589 For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the EDMA3TC decrements BCNT appropriately. For AB-synchronized transfers, BCNTRLD is not used. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 590 You should make sure to program the LINK field correctly, so that link update is requested from a PaRAM address that falls in the range of the available PaRAM addresses on the device. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 591: Dummy And Null Transfer Request
A link update occurs when the PaRAM set is exhausted, as described in Section 17.2.3.7. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 592: Parameter Updates In Edma3Cc (For Non-Null, Non-Dummy Param Set)
You should ensure that no transfer is allowed to cross internal port boundaries between peripherals. A single TR must target a single source/destination slave endpoint. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 593 8 PaRAM words are updated before the new QDMA event can trigger the transfer for that PaRAM entry. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 594 ACNT = 2 (2 bytes) and BCNT = 256. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 595: Linked Transfer Example
Parameter set 2 01C0 4060h Parameter set 3 Link=FFFFh 01C0 4FC0h Parameter set 126 1CA0 4FE0h Parameter set 127 SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 596: Link-To-Self Transfer Example
01C0 4FC0h Parameter set 126 DSTCIDX X SRCCIDX X 1CA0 4FE0h Parameter set 127 Rsvd CCNT X Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 597: Initiating A Dma Transfer
For the synchronization events associated with each of the programmable DMA channels, see your device-specific data manual to determine the event to channel mapping. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 598 NOTE: Chained event registers, event registers, and event set registers operate independently. An event (En) can be triggered by any of the trigger sources (event-triggered, manually- triggered, or chain-triggered). Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 599 QDMA event and initiate another set of transfers as specified by the linked set. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 600: Completion Of A Dma Transfer
There are three ways the EDMA3CC gets updated/informed about a transfer completion: normal completion, early completion, and dummy/null completion. This applies to both chained events and completion interrupt generation. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 601: Event, Channel, And Param Mapping
(unused), that channel can be used for manually-triggered or chained-triggered transfers, for linking/reloading, or as a QDMA channel. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 602: Edma3 Dma Channel To Param Mapping
Reload/QDMA PaRAM Set n - 2 Reload/QDMA PaRAM Set n - 1 Reload/QDMA PaRAM Set n Reload/QDMA Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 603: Qdma Channel To Param Mapping
Parameter set n Note: n is the number of PaRAM sets supported in the EDMA3CC for a specific device. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 604: Edma3 Channel Controller Regions
Table 17-6. Shadow Region Registers DRAEm QRAEm QEER QEECR QEESR EECR EESR SECR IECR IESR Register not affected by DRAE IEVAL Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 605: Shadow Region Registers
DRAE/QRAE registers. If exclusive access to any given channel/TCC code is required for a region, then only that region's DRAE/QRAE should have the associated bit set. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 606: Chaining Edma3 Channels
5 (All TRs) 17.2.9 EDMA3 Interrupts The EDMA3 interrupts are divided into 2 categories: • Transfer completion interrupts Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 607: Edma3 Transfer Completion Interrupts
0 to 31 so that it sets the appropriate bits (0 to 31) in IPR (and can interrupt the CPU(s) on enabling the IER register bits (0-31)). SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 608: Transfer Complete Code (Tcc) To Edma3Cc Interrupt Mapping
(IPR) and single set of interrupt enable registers (IER). A second level of interrupt masking is provided by the programmable DMA region access enable registers (DRAE). See Figure 17-12. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 609: Interrupt Diagram
1 to the corresponding bit in the interrupt pending clear register (ICR). For example, a write of 1 to ICR.E0 clears a pending interrupt in IPR.E0. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 610 Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 611 NOTE: While using IEVAL for shadow region completion interrupts, you should make sure that the IEVAL operated upon is from that particular shadow region memory map. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 612: Error Interrupt Operation
EDMA3_ _CC0_ERRINT Note: n is the number of queues supported in the EDMA3CC for a specific device. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 613: Event Queue(S)
EDMA3TC. In this case, the event is not logged in the event queue status registers. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 614 (CCERR) and the THRXCD bit in QSTATn, where n stands for the event queue number. Any bits that are set in CCERR also generate an EDMA3CC error interrupt. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 615: Edma3 Transfer Controller (Edma3Tc)
16 bytes 16 bytes 16 bytes Error interrupt EDMA3_0_TC0_ERRINT EDMA3_0_TC1_ERRINT EDMA3_1_TC0_ERRINT EDMA3 channel controller EDMA3_0_CC0 EDMA3_0_CC0 EDMA3_1_CC0 used SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 616 TR pipelining is useful for maintaining throughput on back-to-back small TRs. It eliminates the read overhead because reads start in the background of a previous TR writes. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 617 FIFO register entry 3 and the second pending TR is read from the destination FIFO register entry 0. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 618: Event Dataflow
10. This continues until the TR completes and on receiving the acknowledgement signal from the destination slave end point, the EDMA3TCn then signals completion status to the EDMA3CC. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 619: Edma3 Prioritization
QDMA trigger Completion detection From EDMA3TC(s) Error Completion detection interrupt EDMA3 channel controller Error Interrupt Transfer Completion Interrupts SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 620 EDMA3CC memory-map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the System Configuration Module. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 621: Edma3Cc And Edma3Tc Performance And System Considerations
TC will end up issuing several ACNT byte (4 byte) size commands to complete the transfers, which will result in inefficient usage of the read/write buses. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 622: Edma3 Operating Frequency (Clock Control)
DMA channel associated with the peripheral (clearing the EER bit for the channel), then disable the EDMA3CC, and finally disable the EDMA3TC(s). Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 623: Emulation Considerations
1180 0000h 245 246 247 248 245 246 247 249 250 251 252 253 254 253 254 255 SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 624: Block Move Example Param Configuration
(b) Channel Options Parameter (OPT) Content 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0000 0000 TCCMOD FWID Reserved STATIC SYNCDIM Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 625: Subframe Extraction Example
(b) Channel Options Parameter (OPT) Content 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0000 0000 TCCMOD FWID Reserved STATIC SYNCDIM SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 626: Data Sorting Example
C_1023 C_1024 D_1022 D_1023 D_1024 A_1022 B_1022 C_1022 D_1022 A_1023 B_1023 C_1023 D_1023 A_1024 B_1024 C_1024 D_1024 Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 627: Data Sorting Example Param Configuration
(b) Channel Options Parameter (OPT) Content 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0000 0000 TCCMOD FWID Reserved STATIC SYNCDIM SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 628: Peripheral Servicing Example
0. Figure 17-21. Servicing Incoming McBSP Data Example 1180 0000h REVT 01D0 0000h Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 629: Servicing Incoming Mcbsp Data Example Param
(b) Channel Options Parameter (OPT) Content 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0000 0000 TCCMOD FWID Reserved STATIC SYNCDIM SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 630: Servicing Peripheral Burst Example
(b) Channel Options Parameter (OPT) Content 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0000 0000 TCCMOD FWID Reserved STATIC SYNCDIM Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 631: Servicing Continuous Mcbsp Data Example
A1..B1..A2..B2..A3..B3..A4..B4..A5..B5 01D0 0004h A9i A10i A11i A12i A13i 1180 1080h B7o B8o B9o B10o B11o B12o B13o SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 632: Servicing Continuous Mcbsp Data Example Param
Figure 17-27. Servicing Continuous McBSP Data Example Reload PaRAM (a) EDMA Reload Parameters (PaRAM Set 64) for Receive Channel Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 633 (d) Channel Options Parameter (OPT) Content for Transmit Channel (PaRAM Set 65) 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0001 0000 TCCMOD FWID Reserved STATIC SYNCDIM SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 634 The only differences are the link address provided and the address of the data buffer. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 635: Ping-Pong Buffering For Mcbsp Data Example
1180 1080h 1180 1880h B9o B10o B11o B12o B13o B9o B10o B11o B12o B13o A1..B1..A2..B2..A3..B3..A4..B4..A5..B5 01D0 0004h SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 636: Ping-Pong Buffering For Mcbsp Example Param
Figure 17-30. Ping-Pong Buffering for McBSP Example Pong PaRAM (a) EDMA Pong Parameters for Channel 3 at Set 64 Linked to Set 65 Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 637: Ping-Pong Buffering For Mcbsp Example Ping Param
0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h 0001h Reserved Count for 3rd Dimension (CCNT) SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 638 Figure 17-34 shows the EDMA3 setup and illustration of the broken up smaller packet transfers. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 639: Intermediate Transfer Completion Chaining Example
BCNT = 1 CCNT = 1 1D transfer of 16 KByte elements OPT.ITCINTEN = 0 OPT.TCC = Don’t care SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 640: Registers
Link Address/B Count Reload Section 17.4.1.6 SRC_DST_CIDX Source C Index/Destination C Index Section 17.4.1.7 CCNT C Count Section 17.4.1.8 Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 641: Channel Options Parameter (Opt)
CPU, the corresponding IER[TCC] bit must be set to 1. Reserved Reserved. Always write 0 to this bit. Reserved Reserved SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 642 (INCR) mode (SAM/DAM = 0) by appropriately programming the count and indices values. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 643: Channel Source Address Parameter (Src)
0-FFFFh A count for 1st Dimension. Unsigned value specifying the number of contiguous bytes within an array (first dimension of the transfer). Valid values range from 1 to 65 535. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 644: Channel Destination Address Parameter (Dst)
Source B index. Signed value specifying the byte address offset between source arrays within a frame (2nd dimension). Valid values range from –32 768 and 32 767. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 645: Link Address/B Count Reload Parameter (Link_Bcntrld)
PaRAM set. The 5 LSBs of the LINK field should be cleared to 0. A value of FFFFh specifies a null link. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 646: Source C Index/Destination C Index Parameter (Src_Dst_Cidx)
C counter. Unsigned value specifying the number of frames in a block, where a frame is BCNT arrays of ACNT bytes. Valid values range from 1 to 65 535. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 647: Edma3 Channel Controller (Edma3Cc) Registers
System Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 648 QDMA Event Enable Set Register — 2090h QSER QDMA Secondary Event Register — 2094h QSECR QDMA Secondary Event Clear Register — Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 649 QDMA Secondary Event Register — 2294h QSECR QDMA Secondary Event Clear Register — 4000h-4FFFh — Parameter RAM (PaRAM) — SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 650: Revision Id Register (Revid)
LEGEND: R = Read only; -n = value after reset; -x = value is indeterminate after reset Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 651: Edma3Cc Configuration Register (Cccfg) Field Descriptions
5h-7h Reserved Reserved Reserved NUM_DMACH 0-7h Number of DMA channels. 0-3h Reserved 32 DMA channels 5h-7h Reserved SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 652: Qdma Channel N Mapping Register (Qchmapn)
Points to the specific PaRAM entry or the trigger word in the PaRAM set pointed to by PAENTRY. A write to the trigger word results in a QDMA event being recognized. Reserved Reserved Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 653: Dma Channel Queue Number Register N (Dmaqnumn)
Q0. 2h-7h Reserved Table 17-28. Bits in DMAQNUMn DMAQNUMn En bit 8-10 12-14 16-18 20-22 24-26 28-30 SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 654: Qdma Channel Queue Number Register (Qdmaqnum)
System Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 655: Event Missed Register (Emr)
Channel 0-31 event missed. En is cleared by writing a 1 to the corresponding bit in the event missed clear register (EMCR). No missed event. Missed event occurred. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 656: Event Missed Clear Register (Emcr)
No effect. Corresponding missed event bit in the event missed register (EMR) is cleared (En = 0). Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 657: Qdma Event Missed Register (Qemr)
Channel 0-7 QDMA event missed. En is cleared by writing a 1 to the corresponding bit in the QDMA event missed clear register (QEMCR). No missed event. Missed event occurred. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 658: Qdma Event Missed Clear Register (Qemcr)
No effect. Corresponding missed event bit in the QDMA event missed register (QEMR) is cleared (En = 0). Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 659: Edma3Cc Error Register (Ccerr)
Queue threshold error for queue 0. QTHRXCD0 is cleared by writing a 1 to the corresponding bit in the EDMA3CC error clear register (CCERRCLR). Watermark/threshold has not been exceeded. Watermark/threshold has been exceeded. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 660: Edma3Cc Error Clear Register (Ccerrclr)
Clears the QTHRXCD0 bit in the EDMA3CC error register (CCERR) and the WM and THRXCD bits in the queue status register 0 (QSTAT0). Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 661: Error Evaluate Register (Eeval)
EDMA3CC error interrupt will be pulsed if any errors have not been cleared in any of the error registers (EMR, QEMR, or CCERR). SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 662: Dma Region Access Enable Register For Region M (Draem)
Enabled interrupt bits for bit n contribute to the generation of a transfer completion interrupt for shadow region m. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 663: Qdma Region Access Enable For Region M (Qraem)
Accesses via region m address space to bit n in any QDMA channel register are allowed. Reads return the value from bit n and writes modify the state of bit n. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 664: Event Queue Entry Registers (Qxey)
Event entry y in queue x. Event number: 0-7h QDMA channel number (0 to 7) 0-1Fh DMA channel/event number (0 to 31) Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 665: Queue N Status Register (Qstatn)
Start pointer. The offset to the head entry of queue n, in units of entries. Always enabled. Legal values are 0 (0th entry) to Fh (15th entry). SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 666: Queue Watermark Threshold A Register (Qwmthra)
Q0. 0-10h The default is 16 (maximum allowed). Disables the threshold errors. 12h-1Fh Reserved Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 667: Edma3Cc Status Register (Ccstat)
TRACTV Transfer request active. Transfer request processing/submission logic is inactive. Transfer request processing/submission logic is active. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 668 No enabled DMA events are active within the EDMA3CC. At least one enabled DMA event (ER and EER, ESR, CER) is active within the EDMA3CC. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 669: Event Register (Er)
EDMA3CC event is asserted. Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 670: Event Clear Register (Ecr)
(ER). A write of 0 has no effect. No effect. EDMA3CC event is cleared in the event register (ER). Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 671: Event Set Register (Esr)
No effect. Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 672: Chained Event Register (Cer)
No effect. Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 673: Event Enable Register (Eer)
Event is enabled. An external event latched in the event register (ER) is evaluated by the EDMA3CC. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 674: Event Enable Clear Register (Eecr)
No effect. Event is enabled. Corresponding bit in the event enable register (EER) is set (En = 1). Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 675: Secondary Event Register (Ser)
Secondary event clear register No effect. Corresponding bit in the secondary event register (SER) is cleared (En = 0). SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 676: Interrupt Enable Register (Ier)
Table 17-52. Interrupt Enable Register (IER) Field Descriptions Field Value Description 31-0 Interrupt enable for channels 0-31. Interrupt is not enabled. Interrupt is enabled. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 677: Interrupt Enable Clear Register (Iecr)
Interrupt enable set for channels 0-31. No effect. Corresponding bit in the interrupt enable register (IER) is set (In = 1). SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 678: Interrupt Pending Register (Ipr)
Interrupt transfer completion code is not detected or was cleared. Interrupt transfer completion code is detected (In = 1, n = EDMA3TC[5:0]). Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 679: Interrupt Clear Register (Icr)
Interrupt clear register for TCC = 0-31. No effect. Corresponding bit in the interrupt pending register (IPR) is cleared (In = 0). SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 680: Interrupt Evaluate Register (Ieval)
For example, writing to the EVAL bit in IEVAL0 pulses the region 0 completion interrupt, but writing to the EVAL bit in IEVAL1 pulses the region 1 completion interrupt. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 681: Qdma Event Register (Qer)
No effect. Corresponding QDMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 682: Qdma Event Enable Register (Qeer)
QDMA channel n is enabled. QDMA events will be recognized and will get latched in the QDMA event register (QER). Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 683: Qdma Event Enable Clear Register (Qeecr)
QDMA event is enabled. Corresponding bit in the QDMA event enable register (QEER) is set (En = 1). SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 684: Qdma Secondary Event Register (Qser)
QDMA event is not currently stored in the event queue. QDMA event is currently stored in event queue. EDMA3CC will not prioritize additional events. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 685: Qdma Secondary Event Clear Register (Qsecr)
Corresponding bit in the QDMA secondary event register (QSER) and the QDMA event register (QER) is cleared (En = 0). SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 686: Edma3 Transfer Controller (Edma3Tc) Registers
Destination FIFO Source Address Register 3 Section 17.4.3.6.14 3C8h DFCNT3 Destination FIFO Count Register 3 Section 17.4.3.6.15 Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 687: Revision Id Register (Revid)
Description 31-0 Peripheral identifier. 4000 3B00h Uniquely identifies the EDMA3TC and the specific revision of the EDMA3TC. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 688: Edma3Tc Configuration Register (Tccfg)
0-7h FIFO size. 32-byte FIFO 64-byte FIFO 128-byte FIFO (for EDMA3TC0 and EDMA3TC1) 256-byte FIFO 4h-7h Reserved Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 689: Edma3Tc Channel Status Register (Tcstat)
Program register set busy. Program set idle and is available for programming by the EDMA3CC. Program set busy. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 690: Error Status Register (Errstat)
EDMA3TC has detected an error at source or destination address. Error information can be read from the error details register (ERRDET). Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 691: Error Enable Register (Erren)
Interrupt enable for bus error (BUSERR). BUSERR is disabled. BUSERR is enabled and contributes to the state of EDMA3TC error interrupt generation. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 692: Error Clear Register (Errclr)
Clears the BUSERR bit in the error status register (ERRSTAT) and clears the error details register (ERRDET). Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 693: Error Details Register (Errdet)
Write addressing error Write privilege error Write timeout error Write data error Dh-Eh Reserved Write exclusive operation error SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 694: Error Interrupt Command Register (Errcmd)
EDMA3TC error line is pulsed if any of the error status register (ERRSTAT) bits are set to 1. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 695: Read Command Rate Register (Rdrate)
8 EDMA3TC cycles between reads. 16 EDMA3TC cycles between reads. 32 EDMA3TC cycles between reads. 5h-7h Reserved SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 696: Source Active Options Register (Saopt)
Priority 0 - Highest priority 1h-6h Priority 1 to priority 6 Priority 7 - Lowest priority Reserved Reserved Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 697: Source Active Source Address Register (Sasrc)
Read command appropriately. Represents the amount of data remaining to be Read. It should be 0 when transfer request (TR) is complete. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 698: Source Active Destination Address Register (Sadst)
B-Index offset between source arrays. Represents the offset in bytes between the starting address of each source array. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 699: Source Active Memory Protection Proxy Register (Sampprxy)
For any other master that sets up the PaRAM entry. If CPU sets up the PaRAM entry. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 700: Source Active Count Reload Register (Sacntrld)
31-0 SADDRBREF 0-FFFF FFFFh Source address B-reference. Represents the starting address for the array currently being Read. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 701: Source Active Destination Address B-Reference Register (Sadstbref)
A-count reload value. Represents the originally programmed value of ACNT. The reload value is used to reinitialize ACNT after each array is serviced. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 702: Destination Fifo Set Source Address B-Reference Register (Dfsrcbref)
Destination address reference for the destination FIFO register set. Represents the starting address for the array currently being written. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 703: Destination Fifo Options Register N (Dfoptn)
Increment (INCR) mode. Source addressing within an array increments. Constant addressing (CONST) mode. Source addressing within an array wraps around upon reaching FIFO width. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 704: Destination Fifo Source Address Register N (Dfsrcn)
0-FFFFh A-dimension count. Number of bytes to be transferred in first dimension count/count remaining for destination register set. Represents the amount of data remaining to be written. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 705: Destination Fifo Destination Address Register N (Dfdstn)
B-Index offset between source arrays. Represents the offset in bytes between the starting address of each source array. Always Read as 0. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 706: Destination Fifo Memory Protection Proxy Register N (Dfmpprxyn)
For any other master that sets up the PaRAM entry If CPU sets up the PaRAM entry Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 707: Tips
31), make sure that DRAE.E31 is also set for a shadow region completion interrupt because the interrupt pending register bit set will be IPR.I31. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 708: Miscellaneous Programming/Debug Tips
EDMA3CC and EDMA3TC. The EDMA3CC status register (CCSTAT) and the EDMA3TC channel status register (TCSTAT) should be used. Enhanced Direct Memory Access (EDMA3) Controller SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 709: Setting Up A Transfer
ICR before the next set of transfers is performed for the same transfer completion code values. SPRUH82C – April 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 710: Emac/Mdio Module
(PHY) device Management Data Input/Output (MDIO) module integrated in the device..........................Topic Page ..................... 18.1 Introduction ..................... 18.2 Architecture ......................18.3 Registers EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 711: Introduction
Programmable interrupt logic permits the software driver to restrict the generation of back-to-back interrupts, which allows more work to be performed in a single call to the interrupt service routine. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 712: Functional Block Diagram
8K CPPI DMA Bus Master Interrupt Interrupts Combiner Register Bus EMAC MDIO Interrupts Interrupts EMAC MDIO Module Module MII/RMII Bus MDIO Bus EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 713: Industry Standard(S) Compliance Statement
(also known as a switch) with a dedicated LAN connecting each bridge port to a single device. Full-duplex operation constitutes a proper subset of the MAC functionality required for half-duplex operation. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 714: Architecture
MII_RXCLK pins or to the RMII reference clock pin. Data is transmitted and received with respect to the reference clocks of the interface pins. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 715: Memory Map
2.5 MHz MII_TXEN 25 MHz MII_COL MII_CRS Physical System layer MII_RXCLK Transformer core device MII_RXD[3−0] (PHY) MII_RXDV MII_RXER RJ−45 MDIO_CLK MDIO_D SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 716: Emac And Mdio Signals For Mii Interface
PHY address, register address, and data bit cycles. The MDIO_D pin acts as an output for all but the data bit cycles at which time it is an input for read operations. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 717: Ethernet Configuration-Rmii Connections
PHY address, register address, and data bit cycles. The MDIO_D pin acts as an output for all but the data bit cycles at which time it is an input for read operations. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 718: Ethernet Protocol Overview
60 to 1514 bytes of the packet data. Note that this 4-byte field may or may not be included as part of the packet data, depending on how the EMAC is configured. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 719: Programming Interface
Figure 18-5. Basic Descriptor Format Bit Fields Word Offset 16 15 Next Descriptor Pointer Buffer Pointer Buffer Offset Buffer Length Flags Packet Length SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 720: Typical Descriptor Linked List
Packet B Fragment 3 500 bytes −−− pNext (NULL) pBuffer Packet C 1514 1514 bytes SOP | EOP 1514 EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 721 HDP that started the process. This process applies when adding packets to a transmit list, and empty buffers to a receive list. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 722 32-bit boundary that describes a packet or a packet fragment. Example 18-1 shows the transmit buffer descriptor described by a C structure. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 723: Transmit Buffer Descriptor Format
/* Packet Flags */ #define EMAC_DSC_FLAG_SOP 0x80000000u #define EMAC_DSC_FLAG_EOP 0x40000000u #define EMAC_DSC_FLAG_OWNER 0x20000000u #define EMAC_DSC_FLAG_EOQ 0x10000000u #define EMAC_DSC_FLAG_TDOWNCMPLT 0x08000000u #define EMAC_DSC_FLAG_PASSCRC 0x04000000u SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 724 EOP flag. This bit is set by the software application and is not altered by the EMAC. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 725 CRC bytes, as they are part of the valid packet data. Note that this flag is valid on SOP descriptors only. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 726: Receive Buffer Descriptor Format
Buffer Offset Buffer Length Word 3 OWNER TDOWNCMPLT PASSCRC JABBER OVERSIZE FRAGMENT UNDERSIZED CONTROL OVERRUN CODEERROR ALIGNERROR CRCERROR NOMATCH Packet Length EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 727 The range of legal values for the BUFFEROFFSET register is 0 to (Buffer Length – 1) for the smallest value of buffer length for all descriptors in the list. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 728 This would happen under device driver reset or shutdown conditions. The EMAC sets this bit in the descriptor of the first free buffer when the tear down occurs. No additional queue processing is performed. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 729 RXMBPENABLE. Although the packet is a valid Ethernet data packet, it was only received because the EMAC is in promiscuous mode. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 730: Emac Control Module
To arbitrate between the CPU and EMAC buses for access to internal descriptor memory. • To arbitrate between internal EMAC buses for access to system memory. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 731: Mdio Module
• MDIO clock generator • Global PHY detection and link state monitoring • Active PHY monitoring • PHY register user access SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 732: Mdio Module Block Diagram
The user access registers USERACCESSn allows the software to submit the access requests for the PHY connected to the device. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 733 USERACCESSn before initiating a new transaction, to ensure that the previous transaction has completed. The application software can use the ACK bit in USERACCESSn to determine the status of a read transaction. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 734 (USERINTMASKSET), then the bit is also set in the MDIO user command complete interrupt register (USERINTMASKED) and an interrupt is triggered on the CPU. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 735 CSL_FMK(MDIO_USERACCESS0_PHYADR,phyadr) CSL_FMK(MDIO_USERACCESS0_DATA, data) #define PHYREG_wait() while( CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) ) #define PHYREG_waitResults( results ) { while( CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) ); results = CSL_FEXT(MDIO_REGS->USERACCESS0, MDIO_USERACCESS0_DATA); } SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 736: Emac Module
The receive FIFO consists of three cells of 64-bytes each and associated control logic. The FIFO buffers receive data in preparation for writing into packet buffers in device memory. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 737 MAC transmitter then initiates the packet transmission. The SYNC block transmits the packet over the MII or RMII interfaces in accordance with the 802.3 protocol. Transmit statistics are counted by the statistics block. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 738: Mac Interface
(in the following order): 1. An Interpacket Gap (IPG). 2. A 7-byte preamble (all bytes 55h). 3. A 1-byte start of frame delimiter (5Dh). EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 739 00.00h. • Zero padding to 64-byte data length (EMAC transmits only 64-byte pause frames). SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 740 MII_TXEN is deasserted, then 96 bit times (approximately, but not less) is measured from MII_CRS. 18.2.9.2.5 Back Off The EMAC implements the 802.3 binary exponential back-off algorithm. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 741 The MAC operates at 10 Mbps or 100 Mbps, in half-duplex or full-duplex mode, and with or without pause frame support as configured by the host. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 742: Packet Receive Operation
(MACADDRLO). Since all eight MAC addresses share the upper 40 bits of address, MACADDRHI needs to be written only the first time (for the first channel configured). EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 743 The read value is FFFF FFFCh, if the interrupt was due to a teardown command. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 744 64 bytes and the value in the receive maximum length register (RXMAXLEN) bytes in length inclusive and contain no code, align, or CRC errors. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 745: Receive Frame Treatment Summary
No undersized/fragment frames are transferred. All address matching frames with and without errors transferred to the address match channel SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 746: Middle Of Frame Overrun Treatment
OVERRUN flag is set in the SOP buffer descriptor. Note that the RXMAXLEN number of bytes cannot be reached for an overrun to occur (it would be truncated). EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 747: Packet Transmit Operation
(TXnCP) to determine if the interrupt was due to a commanded teardown. The read value is FFFF FFFCh, if the interrupt was due to a teardown command. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 748: Receive And Transmit Latency
5.12 μs. • Any single latency event in request servicing can be no longer than (5.12 × TXCELLTHRESH) μs. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 749: Reset Considerations
MAC status register (MACSTATUS) that gives information about the type of software error that needs to be corrected. For detailed information on error interrupts, see Section 18.2.16.1.4. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 750: Initialization
Also, a PHY can take up to 3 seconds to negotiate a link. Thus, it is advisable to run the MDIO software off a time-based event rather than polling. For more information on PHY control registers, see your PHY device documentation. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 751 TXEN bit in TXCONTROL. Then set the GMIIEN bit in MACCONTROL. 17. Enable the device interrupt in EMAC control module registers CnRXTHRESHEN, CnRXEN, CnTXEN, and CnMISCEN. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 752: Interrupt Support
(RXINTMASKCLEAR). The raw and masked receive interrupt status may be read by reading the receive interrupt status (unmasked) register (RXINTSTATRAW) and the receive interrupt status (masked) register (RXINTSTATMASKED), respectively. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 753 Ownership bit not set in SOP buffer • Zero next buffer descriptor pointer with EOP • Zero buffer pointer • Zero buffer length • Packet length error SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 754 The application software must acknowledge the EMAC control module after receiving MDIO interrupts by writing the appropriate CnMISC key to the EMAC End-Of-Interrupt Vector (MACEOIVECTOR). See Section 18.3.3.12 for the acknowledge key values. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 755 28 interrupt signals: TXPENDn, RXPENDn, RXTHRESHPENDn, STATPEND, HOSTPEND, LINKINT0, and USERINT0. For more details on the interrupt mapping, see the ARM Interrupt Controller (AINTC) chapter. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 756: Power Management
SOFT and FREE bits affect the operation of the emulation suspend. NOTE: Emulation suspend has not been tested. Table 18-7. Emulation Control SOFT FREE Description Normal operation Emulation suspend Normal operation EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 757: Registers
EMAC Control Module Interrupt Core 2 Receive Threshold Section 18.3.1.8 Interrupt Status Register C2RXSTAT EMAC Control Module Interrupt Core 2 Receive Interrupt Section 18.3.1.9 Status Register SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 758: Emac Control Module Revision Id Register (Revid)
Table 18-9. EMAC Control Module Revision ID Register (REVID) Field Descriptions Field Value Description 31-0 Identifies the EMAC Control Module revision. 4EC8 0100h Current revision of the EMAC Control Module. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 759: Emac Control Module Software Reset Register (Softreset)
Software reset bit for the EMAC Control Module. Clears the interrupt status, control registers, and CPPI Ram on the clock cycle following a write of 1. No software reset. Perform a software reset. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 760: Emac Control Module Interrupt Control Register (Intcontrol)
Number of internal EMAC module reference clock periods within a 4 μs time window (see your device-specific data manual for information). EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 761: Emac Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register (Cnrxthreshen)
Enable CnRXTHRESHPULSE interrupt generation for RX Channel 0 CnRXTHRESHPULSE generation is disabled for RX Channel 0. CnRXTHRESHPULSE generation is enabled for RX Channel 0. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 762: Emac Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (Cnrxen)
Enable CnRXPULSE interrupt generation for RX Channel 0 CnRXPULSE generation is disabled for RX Channel 0. CnRXPULSE generation is enabled for RX Channel 0. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 763: Emac Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (Cntxen)
Enable CnTXPULSE interrupt generation for TX Channel 0 CnTXPULSE generation is disabled for TX Channel 0. CnTXPULSE generation is enabled for TX Channel 0. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 764: Emac Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (Cnmiscen)
Enable CnMISCPULSE interrupt generation when MDIO USERINT0 interrupts (corresponding to USERACCESS0) are generated CnMISCPULSE generation is disabled for MDIO USERINT0. CnMISCPULSE generation is enabled for MDIO USERINT0. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 765: Emac Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register (Cnrxthreshstat)
RX Channel 0 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt. RX Channel 0 satisfies conditions to generate a CnRXTHRESHPULSE interrupt. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 766: Emac Control Module Interrupt Core 0-2 Receive Interrupt Status Register (Cnrxstat)
RX Channel 0 does not satisfy conditions to generate a CnRXPULSE interrupt. RX Channel 0 satisfies conditions to generate a CnRXPULSE interrupt. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 767: Emac Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (Cntxstat)
TX Channel 0 does not satisfy conditions to generate a CnTXPULSE interrupt. TX Channel 0 satisfies conditions to generate a CnTXPULSE interrupt. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 768: Emac Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (Cnmiscstat)
Interrupt status for MDIO USERINT0 masked by the CnMISCEN register MDIO USERINT0 does not satisfy conditions to generate a CnMISCPULSE interrupt. MDIO USERINT0 satisfies conditions to generate a CnMISCPULSE interrupt. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 769: Emac Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (Cnrximax)
> 0.5*RXIMAX) pace_counter = previous_pace_counter - 1; else if(interrupt_count != 0) pace_counter = previous_pace_counter/2; else pace_counter = 0; previous_pace_counter = pace_counter; SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 770: Emac Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (Cntximax)
> 0.5*TXIMAX) pace_counter = previous_pace_counter - 1; else if(interrupt_count != 0) pace_counter = previous_pace_counter/2; else pace_counter = 0; previous_pace_counter = pace_counter; EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 771: Mdio Registers
Table 18-23. MDIO Revision ID Register (REVID) Field Descriptions Field Value Description 31-0 Identifies the MDIO Module revision. 0007 0104h Current revision of the MDIO Module. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 772: Mdio Control Register (Control)
MDIO_CLK. MDIO_CLK is disabled when CLKDIV is cleared to 0. MDIO_CLK frequency = peripheral clock frequency/(CLKDIV + 1). EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 773: Phy Acknowledge Status Register (Alive)
The PHY indicates it does not have a link or fails to acknowledge the read transaction The PHY with the corresponding address has a link and the PHY acknowledges the read transaction. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 774: Mdio Link Status Change Interrupt (Unmasked) Register (Linkintraw)
An MDIO link change event (change in the LINK register) corresponding to the PHY address in MDIO user PHY select register USERPHYSEL0 EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 775: Mdio Link Status Change Interrupt (Masked) Register (Linkintmasked)
An MDIO link change event (change in the LINK register) corresponding to the PHY address in MDIO user PHY select register USERPHYSEL0 and the LINKINTENB bit in USERPHYSEL0 is set to 1. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 776: Mdio User Command Complete Interrupt (Unmasked) Register (Userintraw)
No MDIO user command complete event. The previously scheduled PHY read or write command using MDIO user access register USERACCESS0 has completed. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 777: Mdio User Command Complete Interrupt (Masked) Register (Userintmasked)
The previously scheduled PHY read or write command using MDIO user access register USERACCESS0 has completed and the corresponding bit in USERINTMASKSET is set to 1. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 778: Mdio User Command Complete Interrupt Mask Set Register (Userintmaskset)
MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is disabled. MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is enabled. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 779: Mdio User Command Complete Interrupt Mask Clear Register (Userintmaskclear)
MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is enabled. MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is disabled. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 780: Mdio User Access Register 0 (Useraccess0)
0-FFFFh User data bits. These bits specify the data value read from or to be written to the specified PHY register. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 781: Mdio User Phy Select Register 0 (Userphysel0)
Link change status interrupts for PHY address specified in PHYADDRMON bits are enabled. Reserved Reserved PHYADRMON 0-1Fh PHY address whose link status is to be monitored. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 782: Mdio User Access Register 1 (Useraccess1)
0-FFFFh User data bits. These bits specify the data value read from or to be written to the specified PHY register. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 783: Mdio User Phy Select Register 1 (Userphysel1)
Reserved PHY address whose link status is to be monitored. PHYADRMON 0-1Fh PHY address whose link status is to be monitored. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 784: Emac Module Registers
Receive Channel 6 Free Buffer Count Register Section 18.3.3.28 15Ch RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register Section 18.3.3.28 160h MACCONTROL MAC Control Register Section 18.3.3.29 EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 785 Section 18.3.3.49 670h RX4CP Receive Channel 4 Completion Pointer Register Section 18.3.3.49 674h RX5CP Receive Channel 5 Completion Pointer Register Section 18.3.3.49 SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 786 288h RXMOFOVERRUNS Receive FIFO or DMA Middle of Frame Overruns Register Section 18.3.3.50.35 28Ch RXDMAOVERRUNS Receive DMA Overruns Register Section 18.3.3.50.36 EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 787: Transmit Revision Id Register (Txrevid)
Table 18-39. Transmit Control Register (TXCONTROL) Field Descriptions Field Value Description 31-1 Reserved Reserved TXEN Transmit enable Transmit is disabled. Transmit is enabled. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 788: Transmit Teardown Register (Txteardown)
Teardown transmit channel 2 Teardown transmit channel 3 Teardown transmit channel 4 Teardown transmit channel 5 Teardown transmit channel 6 Teardown transmit channel 7 EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 789: Receive Revision Id Register (Rxrevid)
Table 18-42. Receive Control Register (RXCONTROL) Field Descriptions Field Value Description 31-1 Reserved Reserved RXEN Receive enable Receive is disabled. Receive is enabled. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 790: Receive Teardown Register (Rxteardown)
Teardown receive channel 2 Teardown receive channel 3 Teardown receive channel 4 Teardown receive channel 5 Teardown receive channel 6 Teardown receive channel 7 EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 791: Transmit Interrupt Status (Unmasked) Register (Txintstatraw)
TX2PEND TX2PEND raw interrupt read (before mask) TX1PEND TX1PEND raw interrupt read (before mask) TX0PEND TX0PEND raw interrupt read (before mask) SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 792: Transmit Interrupt Status (Masked) Register (Txintstatmasked)
TX4PEND masked interrupt read TX3PEND TX3PEND masked interrupt read TX2PEND TX2PEND masked interrupt read TX1PEND TX1PEND masked interrupt read TX0PEND TX0PEND masked interrupt read EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 793: Transmit Interrupt Mask Set Register (Txintmaskset)
Transmit channel 1 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. TX0MASK Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 794: Transmit Interrupt Mask Clear Register (Txintmaskclear)
Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. TX0MASK Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 795: Mac Input Vector Register (Macinvector)
Receive channels 0-7 interrupt (RXnTHRESHPEND) pending status. Bit 8 is RX0THRESHPEND. RXPEND 0-FFh Receive channels 0-7 interrupt (RXnPEND) pending status bit. Bit 0 is RX0PEND. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 796: Mac End Of Interrupt Vector Register (Maceoivector)
Acknowledge C1MISC Interrupt (STATPEND, HOSTPEND, MDIO LINKINT0, MDIO USERINT0) Acknowledge C2RXTHRESH Interrupt Acknowledge C2RX Interrupt Acknowledge C2TX Interrupt Acknowledge C2MISC Interrupt (STATPEND, HOSTPEND, MDIO LINKINT0, MDIO USERINT0) Ch-1Fh Reserved EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 797: Receive Interrupt Status (Unmasked) Register (Rxintstatraw)
RX2PEND RX2PEND raw interrupt read (before mask) RX1PEND RX1PEND raw interrupt read (before mask) RX0PEND RX0PEND raw interrupt read (before mask) SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 798: Receive Interrupt Status (Masked) Register (Rxintstatmasked)
RX4PEND masked interrupt read RX3PEND RX3PEND masked interrupt read RX2PEND RX2PEND masked interrupt read RX1PEND RX1PEND masked interrupt read RX0PEND RX0PEND masked interrupt read EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 799: Receive Interrupt Mask Set Register (Rxintmaskset)
Receive channel 1 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. RX0MASK Receive channel 0 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 800: Receive Interrupt Mask Clear Register (Rxintmaskclear)
Receive channel 1 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. RX0MASK Receive channel 0 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 801: Mac Interrupt Status (Unmasked) Register (Macintstatraw)
Value Description 31-2 Reserved Reserved HOSTPEND Host pending interrupt (HOSTPEND); masked interrupt read. STATPEND Statistics pending interrupt (STATPEND); masked interrupt read. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 802: Mac Interrupt Mask Set Register (Macintmaskset)
Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. STATMASK Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 803: Receive Multicast/Broadcast/Promiscuous Channel Enable Register (Rxmbpenable)
/ code errors and undersized are short frames without errors. Short frames are filtered. Short frames are transferred to memory. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 804 RXMULTCH bits. Multicast frames are filtered. Multicast frames are copied to the channel selected by RXMULTCH bits. Reserved Reserved EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 805 Select channel 5 to receive multicast frames Select channel 6 to receive multicast frames Select channel 7 to receive multicast frames SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 806: Receive Unicast Enable Set Register (Rxunicastset)
Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May be read. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 807: Receive Unicast Clear Register (Rxunicastclear)
RXCH0EN Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 808: Receive Maximum Length Register (Rxmaxlen)
15 bytes of the buffer are to be ignored by the EMAC and that valid buffer data starts on byte 16 of the buffer. This value is used for all channels. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 809: Receive Filter Low Priority Frame Threshold Register (Rxfilterlowthresh)
Receive flow threshold. These bits contain the threshold value for issuing flow control on incoming frames for channel n (when enabled). SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 810: Receive Channel N Free Buffer Count Register (Rxnfreebuffer)
The host must write this field with the number of buffers that have been freed due to host processing. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 811: Mac Control Register (Maccontrol)
The queue uses a fixed-priority (channel 7 highest priority) scheme to select the next channel for transmission. Reserved Reserved TXPACE Transmit pacing enable bit Transmit pacing is disabled. Transmit pacing is enabled. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 812 FULLDUPLEX bit. The loopback bit should be changed only when GMIIEN bit is deasserted. Loopback mode is disabled. Loopback mode is enabled. FULLDUPLEX Full duplex mode. Half-duplex mode is enabled. Full-duplex mode is enabled. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 813: Mac Status Register (Macstatus)
The host error occurred on transmit channel 5 The host error occurred on transmit channel 6 The host error occurred on transmit channel 7 SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 814 Any transmission in progress when this bit is asserted will complete. Transmit flow control is inactive. Transmit flow control is active. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 815: Emulation Control Register (Emcontrol)
Two 64-byte packet cells required to be in the transmit FIFO. Three 64-byte packet cells required to be in the transmit FIFO. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 816: Mac Configuration Register (Macconfig)
If a 1 is read, the reset has not yet occurred. If a 0 is read, then a reset has occurred. A software reset has not occurred. A software reset has occurred. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 817: Mac Source Address Low Bytes Register (Macsrcaddrlo)
MAC source address bits 31-24 (byte 3) 15-8 MACSRCADDR4 0-FFh MAC source address bits 39-32 (byte 4) MACSRCADDR5 0-FFh MAC source address bits 47-40 (byte 5) SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 818: Mac Hash Address Register 1 (Machash1)
Most-significant 32 bits of the hash table corresponding to hash values 32 to 63. If a hash table bit is set, then a group address that hashes to that bit index is accepted. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 819: Back Off Random Number Generator Test Register (Bofftest)
IPG time is not stretched to four times the normal value. Transmit pacing helps reduce capture effects, which improves overall network bandwidth. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 820: Receive Pause Timer Register (Rxpause)
The transmit pause timer is loaded by a received (incoming) pause frame, and then decremented at slot time intervals down to 0, at which time EMAC transmit frames are again enabled. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 821: Mac Address Low Bytes Register (Macaddrlo)
MATCHFILT is cleared to 0. 15-8 MACADDR0 0-FFh MAC address lower 8-0 bits (byte 0) MACADDR1 0-FFh MAC address bits 15-8 (byte 1) SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 822: Mac Address High Bytes Register (Macaddrhi)
16 bits of the address to the MACADDRLO register. Since all eight addresses share the upper 40 bits of the address, the MACADDRHI register only needs to be written the first time. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 823: Transmit Channel N Dma Head Descriptor Pointer Register (Txnhdp)
Writing to these locations when they are nonzero is an error (except at reset). Host software must initialize these locations to 0 on reset. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 824: Transmit Channel N Completion Pointer Register (Txncp)
The EMAC uses the value written to determine if the interrupt should be deasserted. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 825: Statistics Register
Had no CRC error, alignment error, or code error Section 18.2.5.5 for definitions of alignment, code, and CRC errors. Overruns have no effect on this statistic. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 826 Overruns have no effect on this statistic. CRC alignment or code errors can be calculated by summing receive alignment errors, receive code errors, and receive CRC errors. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 827 The address matching process decided that the frame should be discarded (filtered) because it did not match the unicast, broadcast, or multicast address, and it did not match due to promiscuous mode. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 828 Any data or MAC control frame that was destined for any unicast, broadcast, or multicast address • Was any length • Had no late or excessive collisions, no carrier loss, and no underrun EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 829 When the EMAC is in half-duplex mode, flow control is active, and a frame reception begins. CRC errors have no effect on this statistic. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 830 The number of frames sent by the EMAC that experienced FIFO underrun. Late collisions, CRC errors, carrier loss, and underrun have no effect on this statistic. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 831 Was 128-bytes to 255-bytes long CRC errors, alignment/code errors, underruns, and overruns do not affect the recording of frames in this statistic. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 832 The objective of this statistic is to give a reasonable indication of Ethernet utilization. EMAC/MDIO Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 833 (zero head descriptor pointer at the start or during the middle of the frame reception). CRC errors, alignment errors, and code errors have no effect on this statistic. SPRUH82C – April 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 834: External Memory Interface A (Emifa)
EMIFA SDRAM is supported on your device..........................Topic Page ..................... 19.1 Introduction ..................... 19.2 Architecture ..................19.3 Example Configuration ......................19.4 Registers External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 835: Introduction
The EMIFA SDRAM interface is not supported on all devices, see your device-specific data manual to see if the EMIFA SDRAM is supported on your device. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 836: Clock Control
When interfacing to an asynchronous device, this pin provides a signal which is active-low during the strobe period of an asynchronous write access cycle. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 837: Emifa Pins Specific To Sdram
EMIFA asynchronous read/write control. This pin stays high during reads and stays low during writes (same duration as CS). SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 838: Sdram Controller And Interface
EMA_A[12:11] EMA_A[10] EMA_A[9:0] Bank/X ACTV Bank READ Bank Column Column Bank Column Column Mode Mode Mode REFR SLFR External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 839: Timing Waveform Of Sdram Pre Command
16-bit interface, refer to Table 19-6 for list of commonly-supported SDRAM devices and the required connections for the address pins. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 840: Emifa To 2M × 16 × 4 Bank Sdram Interface
128M bits ×16 SDRAM A[11:0] EMIFA EMA_A[11:0] 256M bits SDRAM A[12:0] EMIFA EMA_A[12:0] 512M bits SDRAM A[12:0] EMIFA EMA_A[12:0] External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 841: Description Of The Sdram Configuration Register (Sdcr)
/ (Required SDRAM Refresh Rate) EMA_CLK More information about the operation of the SDRAM refresh controller can be found in Section 19.2.4.6. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 842: Description Of The Sdram Timing Register (Sdtimr)
(a) Issuing a PRE command with EMA_A[10] held high if any banks are open (b) Issuing an REF command External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 843: Sdram Load Mode Register Command
2. Program SDTIMR and SDSRETR to satisfy the timing requirements for the attached SDRAM device. The timing parameters should be taken from the SDRAM datasheet. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 844: Refresh Urgency Levels
Refresh Release urgency level is reached. At that point, the EMIFA can begin servicing any new read or write requests. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 845 EMA_CLK using the PLL Controller. If the frequency of EMA_CLK changes while the SDRAM is not in Self-Refresh Mode, Procedure B in Section 19.2.4.5 should be followed to reinitialize the device. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 846 If the PD bit is cleared while in the power-down state, the EMIFA will come out of the power-down state. The EMIFA: • Drives EMA_SDCKE high. • Enters its idle state. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 847: Timing Waveform For Basic Sdram Read Operation
NOP commands between various commands during an access. Refer to the register description of SDTIMR in Section 19.4.6 for more details on the various timing parameters. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 848: Timing Waveform For Basic Sdram Write Operation
NOP commands during various cycles of an access. Refer to the register description of SDTIMR in Section 19.4.6 for more details on the various timing parameters. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 849: Mapping From Logical Address To Emifa Pins For 16-Bit Sdram
NOTE: The upper bit of the Row Address is used only when addressing 256-Mbit and 512-Mbit SDRAM memories. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 850: Asynchronous Controller And Interface
EMA_CS[n], n = 2, 3, 4, or 5. Figure 19-7. EMIFA Asynchronous Interface EMIFA EMA_CS[n] EMA_WE EMA_OE EMA_WAIT EMA_D[x:0] EMA_WE_DQM[x:0] EMA_A[x:0] EMA_BA[1:0] External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 851: Emifa To 8-Bit/16-Bit Memory Interface
EMIF to 16-bit memory interface Figure 19-9. Common Asynchronous Interface EMIFA 16−bit asynchronous device EMA_CS[n] EMA_WE EMA_WE_DQM[1:0] BE[1:0] EMA_D[15:0] DQ[15:0] SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 852: Description Of The Asynchronous M Configuration Register (Cencfg)
The EMA_WAIT pin is not available on all devices; therefore, this field is reserved on those devices. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 853: Description Of The Asynchronous Wait Cycle Configuration Register (Awcc)
NAND Flash Mode. The EMA_WAIT pin is not available on all devices; therefore, this register is reserved on those devices. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 854 EMIFA interrupts. Extended Wait Mode should not be used while in NAND Flash Mode. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 855: Description Of The Emifa Interrupt Mask Set Register (Intmskset)
If so, the EMIFA proceeds to the setup period of the operation. If it is no longer the highest priority task, the EMIFA terminates the operation. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 856: Timing Waveform Of An Asynchronous Read Cycle In Normal Mode
Figure 19-10. Timing Waveform of an Asynchronous Read Cycle in Normal Mode Strobe Setup Hold EMA_CLK EMA_CS[n] EMA_WE_DQM Byte enable EMA_A/EMA_BA Address EMA_D Data EMA_OE EMA_WE External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 857: Asynchronous Write Operation In Normal Mode
If this is the case, the EMIFA instead enters directly into the turnaround period for the pending read or write operation. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 858: Timing Waveform Of An Asynchronous Write Cycle In Normal Mode
Figure 19-11. Timing Waveform of an Asynchronous Write Cycle in Normal Mode Strobe Setup Hold EMA_CLK EMA_CS[n] EMA_WE_DQM Byte enable EMA_A/EMA_BA Address Address EMA_D Data EMA_OE EMA_WE External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 859: Asynchronous Read Operation In Select Strobe Mode
If this is the case, the EMIFA instead enters directly into the turnaround period for the pending read or write operation. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 860: Timing Waveform Of An Asynchronous Read Cycle In Select Strobe Mode
Figure 19-12. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode Strobe Setup Hold EMA_CLK EMA_CS[n] EMA_WE_DQM Byte enables EMA_A/EMA_BA Address EMA_D Data EMA_OE EMA_WE External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 861: Asynchronous Write Operation In Select Strobe Mode
If this is the case, the EMIFA instead enters directly into the turn-around period for the pending read or write operation. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 862: Timing Waveform Of An Asynchronous Write Cycle In Select Strobe Mode
Figure 19-13. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode Strobe Setup Hold EMA_CLK EMA_CS[n] EMA_WE_DQM Byte enables EMA_A/EMA_BA Address EMA_D Data EMA_OE EMA_WE External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 863: Description Of The Nand Flash Control Register (Nandfcr)
NOTE: The EMIFA will not control the NAND Flash device's write protect pin. The write protect pin must be controlled outside of the EMIFA. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 864: Emifa To Nand Flash Interface
See Section 19.2.5.6.8 for workaround. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 865 5) bit. Figure 19-15 shows the algorithm used to calculate the ECC value for an 8-bit NAND Flash. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 866: Ecc Value For 8-Bit Nand Flash
If bit errors fall into more than four bytes, the ECC engine will report that there are too many errors to correct. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 867 XORing the error word with the error value from the NAND Flash error value 1-2 registers (NANDERRVAL[2:1]). SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 868 R_SETUP and R_STROBE fields must be greater than 4 for the EMIFA to recognize the EMA_WAIT pin has been asserted. The W_SETUP, W_STROBE, R_SETUP, and R_STROBE fields are in CEnCFG. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 869: Data Bus Parking
Figure 19-16. EMIFA Reset Block Diagram EMIFA CHIP_RST Hard Reset Memory from PLL Controller Registers State MOD_G_RST EMIFA Machine SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 870: Interrupt Support
See Section 19.4 for complete details on the register fields. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 871: Edma Event Support
For details on EMIFA pin multiplexing, see your device-specific data manual. 19.2.11 Memory Map For information describing the device memory-map, see your device-specific data manual. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 872: Priority And Arbitration
See Section 19.2.4.7 for details on the operation of the EMIFA when in the self-refresh state. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 873: System Considerations
The system should be analyzed to make sure that this worst-case request delay is acceptable. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 874: Power Management
EMA_SDCKE remains low until any request arrives. Refer to Section 19.2.4.8 for more details on placing EMIFA in power down mode. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 875: Emulation Considerations
19.2.15 Emulation Considerations EMIFA memory controller will remain fully functional during emulation halts, to allow emulation access to external memory. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 876: Example Configuration
Table 19-26. SR Field Value For the EMIFA to K4S641632H-TC(L)70 Interface Field Value Purpose 1 then 0 To place the EMIFA into the self refresh state External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 877: Example Configuration Interface
EMA_A[18:0] A[11:0] LDQM EMA_WE_DQM[0] UDQM EMA_WE_DQM[1] DQ[15:0] EMA_D[15:0] EMA_CS[3] EMA_OE TC5515100FT-12 EMA_WAIT A[0] A[19:1] DQ[15:0] RY/BY BYTE0 BYTE1 SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 878: Sdram Timing Register (Sdtimr)
Figure 19-19. SDRAM Timing Register (SDTIMR) 0 0110 T_RFC T_RP Rsvd T_RCD Rsvd T_WR 0100 0110 0000 T_RAS T_RC Rsvd T_RRD Reserved External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 879: Sdram Self Refresh Exit Timing Register (Sdsretr)
Figure 19-21. SDRAM Refresh Control Register (SDRCR) 0 0000 0000 0000 Reserved Reserved 0 0110 0001 1010 (61Ah) Reserved SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 880: Sdram Configuration Register (Sdcr)
0 0000 Reserved Reserved Reserved 00 0000 Reserved Reserved Reserved Reserved Reserved Reserved BIT11_9LOCK Reserved IBANK Reserved PAGESIZE External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 881: Emifa Input Timing Requirements
R_SETUP width in EMIFA clock cycles minus 1 cycle. R_SETUP + R_STROBE ≥ R_SETUP ) R_STROBE ) R_HOLD w R_HOLD w SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 882: Timing Waveform Of An Asram Read
Address valid to end of Write Data Setup time Write Recovery time Data Hold time Write Cycle time External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 883: Timing Waveform Of An Asram Write
W_SETUP ) W_STROBE ) W_HOLD w Figure 19-24. Timing Waveform of an ASRAM Write Setup Hold Strobe EMA_CS[n] EMA_A[x:0] EMA_BA[1:0] EMA_WE EMA_D[x:0] SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 884: Asram Timing Requirements With Pcb Delays
R_SETUP ) R_STROBE ) R_HOLD w (m) * t EM_D EM_A R_HOLD w (m) ) t EM_CS EM_D TA w External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 885: Timing Waveform Of An Asram Read With Pcb Delays
CEnCFG is programmed in terms of EMIFA clock cycles, minus 1 cycle. For example, W_SETUP is equal to W_SETUP width in EMIFA clock cycles minus 1 cycle. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 886: Timing Waveform Of An Asram Write With Pcb Delays
EMA_CS[n] (ASRAM) EMA_A[x:0]/ EMA_BA[1:0] EMA_A EMA_A EMA_A[x:0]/ EMA_BA[1:0] (ASRAM) EMA_WE EMA_WE EMA_WE EMA_WE (ASRAM) EMA_D[x:0] EMA_D EMA_D EMA_D[x:0] (ASRAM) External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 887: Emifa Timing Requirements For Tc5516100Ft-12 Example
Delay on EMA_WE from EMIFA to ASRAM. EMA_WE is driven by EMIF. 0.36 EM_WE Delay on EMA_D from EMIFA to ASRAM. EMA_D is driven by EMIF. 0.45 EM_D SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 888 * 3 w * 3 w * 1.8 Therefore, W_SETUP = 0, W_STROBE = 0, and W_HOLD = 0. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 889: Configuring Ce3Cfg For Tc5516100Ft-12 Example
Recommended Margin Output Setup 10 nS Output Hold 10 nS Input Setup 10 nS Input Hold 10 nS SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 890: Emifa Read Timing Requirements
EMIFA and NAND Flash AC timing requirements work together to define the values for R_SETUP, R_STROBE, and R_HOLD. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 891: Timing Waveform Of A Nand Flash Read
TA w max Figure 19-27. Timing Waveform of a NAND Flash Read Setup Hold Strobe EMA_CS[n] ALE_EM_A[1] CLE_EM_A[2] EMA_OE EMA_D[7:0] SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 892: Nand Flash Write Timing Requirements
W_SETUP w max W_STROBE w W_SETUP + W_STROBE ≥ W_HOLD w max W_SETUP ) W_STROBE ) W_HOLD w External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 893: Timing Waveform Of A Nand Flash Command Write
Figure 19-29. Timing Waveform of a NAND Flash Address Write Setup Hold Strobe EMA_CS[n] ALE_EM_A[1] CLE_EM_A[2] EMA_WE EMA_D[7:0] SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 894: Timing Waveform Of A Nand Flash Data Write
Figure 19-30. Timing Waveform of a NAND Flash Data Write Setup Hold Strobe EMA_CS[n] ALE_EM_A[1] CLE_EM_A[2] EMA_WE EMA_D[7:0] External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 895: Emifa Timing Requirements For Hy27Ua081G1M Example
Data Setup time CLE Hold time ALE Hold time CS Hold time Data Hold time Write Cycle time SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 896 Therefore with a 10 nS margin added in, W_SETUP ≥ 0, W_STROBE ≥ 6, and W_HOLD ≥ 1. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 897: Configuring Ce2Cfg For Hy27Ua081G1M Example
• CS3NAND = 0. NAND Flash mode is disabled. CS2NAND NAND Flash mode for chip select 2. • CS5NAND = 1. NAND Flash mode is enabled. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 898: Registers
NAND Flash 4-Bit ECC Error Value Register 1 Section 19.4.22 NANDERRVAL2 NAND Flash 4-Bit ECC Error Value Register 2 Section 19.4.23 External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 899: Module Id Register (Midr)
R/W-0 R/W-0 Reserved MAX_EXT_WAIT R/W-80h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 900: Asynchronous Wait Cycle Configuration Register (Awccr) Field Descriptions
× 16 clock cycles before it stops inserting asynchronous wait cycles and proceeds to the hold period of the access. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 901: Sdram Configuration Register (Sdcr)
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default value of 0. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 902 10 column address bits (1024 elements per row) 11 column address bits (2048 elements per row) 4h-7h Reserved External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 903: Sdram Refresh Control Register (Sdrcr)
Writing a value < 0x0020 to this field will cause it to be loaded with (2 × T_RFC) + 1 value from the SDRAM timing register (SDTIMR). SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 904: Asynchronous N Configuration Registers (Ce2Cfg-Ce5Cfg)
Read setup width in the format n - 1, where n = number of EMA_CLK cycles. See Section 19.2.5.3 details. 0h = Divide-by-1 1h = Divide-by-2 … 2h – 1Fh = Divide-by-3 to Divide-by-16 External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 905 Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. 8-bit data bus 16-bit data bus 2h-3h Reserved SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 906: Sdram Timing Register (Sdtimr)
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default value of 0. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 907: Sdram Self Refresh Exit Timing Register (Sdsretr)
This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command, minus one. T_XS = Txsr / t EMA_CLK SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 908: Emifa Interrupt Raw Register (Intraw)
Indicates that an Asynchronous Timeout has occurred. Writing a 1 will clear this bit as well as the AT_MASKED bit in the EMIFA interrupt masked register (INTMSK). External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 909: Emifa Interrupt Masked Register (Intmsk)
Indicates that an Asynchronous Timeout Interrupt has been generated. Writing a 1 will clear this bit as well as the AT bit in the EMIFA interrupt raw register (INTRAW). SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 910: Emifa Interrupt Mask Set Register (Intmskset)
Indicates that the Asynchronous Timeout Interrupt is enabled. Writing a 1 sets this bit and the AT_MASK_CLR bit in the EMIFA interrupt mask clear register (INTMSKCLR). External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 911: Emifa Interrupt Mask Clear Register (Intmskclr)
Indicates that the Asynchronous Timeout Interrupt is enabled. Writing a 1 clears this bit and the AT_MASK_SET bit in the EMIFA interrupt mask set register (INTMSKSET). SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 912: Nand Flash Control Register (Nandfcr)
Do not start ECC calculation. Start ECC calculation on data for NAND Flash on EMA_CS2. Reserved Reserved External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 913 Using NAND Flash on EMA_CS3. CS2NAND NAND Flash mode for chip select 2. Not using NAND Flash. Using NAND Flash on EMA_CS2. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 914: Nand Flash Status Register (Nandfsr)
(AWCC) has no effect on WAITST. EMA_WAIT[n] pin is low. EMA_WAIT[n] pin is high. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 915: Nand Flash N Ecc Registers (Nandf1Ecc-Nandf4Ecc)
ECC code calculated while reading/writing NAND Flash. ECC code calculated while reading/writing NAND Flash. ECC code calculated while reading/writing NAND Flash. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 916: Nand Flash 4-Bit Ecc Load Register (Nand4Biteccload)
0-3FFh 4-bit ECC load. This value is used to load the ECC values when performing the Syndrome calculation during reads. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 917: Nand Flash 4-Bit Ecc Register 1 (Nand4Bitecc1)
0-3FFh Calculated 4-bit ECC or Syndrom Value4. 15-10 Reserved Reserved 4BITECCVAL3 0-3FFh Calculated 4-bit ECC or Syndrom Value3. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 918: Nand Flash 4-Bit Ecc Register 3 (Nand4Bitecc3)
0-3FFh Calculated 4-bit ECC or Syndrom Value8. 15-10 Reserved Reserved 4BITECCVAL7 0-3FFh Calculated 4-bit ECC or Syndrom Value7. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 919: Nand Flash 4-Bit Ecc Error Address Register 1 (Nanderradd1)
0-3FFh Calculated 4-bit ECC Error Address 4. 15-10 Reserved Reserved 4BITECCERRADD3 0-3FFh Calculated 4-bit ECC Error Address 3. SPRUH82C – April 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 920: Nand Flash 4-Bit Ecc Error Value Register 1 (Nanderrval1)
0-3FFh Calculated 4-bit ECC Error Value 4. 15-10 Reserved Reserved 4BITECCERRVAL3 0-3FFh Calculated 4-bit ECC Error Value 3. External Memory Interface A (EMIFA) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 921: General-Purpose Input/Output (Gpio)
This chapter describes the GPIO..........................Topic Page ..................... 20.1 Introduction ..................... 20.2 Architecture ......................20.3 Registers SPRUH82C – April 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 922: Introduction
The GPIO peripheral connects to external devices. While it is possible that the software implements some standard connectivity protocol over GPIO, the GPIO peripheral itself is not compliant with any such standards. General-Purpose Input/Output (GPIO) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 923: Architecture
20.2.4 Endianness Considerations The GPIO operation is independent of endianness; therefore, there are no endianness considerations for the GPIO module. SPRUH82C – April 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 924: Gpio Register Structure
GP1[10] register_name01 Bit 26 GP1P10 GP1[11] register_name01 Bit 27 GP1P11 GP1[12] register_name01 Bit 28 GP1P12 GP1[13] register_name01 Bit 29 GP1P13 General-Purpose Input/Output (GPIO) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 925 GP4[9] register_name45 Bit 9 GP4P9 GP4[10] register_name45 Bit 10 GP4P10 GP4[11] register_name45 Bit 11 GP4P11 GP4[12] register_name45 Bit 12 GP4P12 SPRUH82C – April 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 926 GP7[8] register_name67 Bit 24 GP7P8 GP7[9] register_name67 Bit 25 GP7P9 GP7[10] register_name67 Bit 26 GP7P10 GP7[11] register_name67 Bit 27 GP7P11 General-Purpose Input/Output (GPIO) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 927: Using A Gpio Signal As An Output
GPIO input data register (IN_DATA) associated with the desired GPIO signal. IN_DATA contains the actual logic state on the external signal. For detailed information on these registers, see Section 20.3. SPRUH82C – April 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 928: Using A Gpio Signal As An Input
PSC reset, followed by GPIO clock enable) will result in the default configuration register settings. For details on the PSC, see the Power and Sleep Controller (PSC) chapter. General-Purpose Input/Output (GPIO) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 929: Initialization
Write a logic 1 to the associated bit in SET_FAL_TRIG. • Write a logic 1 to the associated bit in CLR_RIS_TRIG. SPRUH82C – April 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 930: Edma Event Support
20.2.13 Emulation Considerations The GPIO peripheral is not affected by emulation suspend events (such as halts and breakpoints). General-Purpose Input/Output (GPIO) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 931: Registers
GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register Section 20.3.11 INTSTAT45 GPIO Banks 4 and 5 Interrupt Status Register Section 20.3.12 SPRUH82C – April 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 932: Revision Id Register (Revid)
LEGEND: R = Read only; -n = value after reset Table 20-3. Revision ID Register (REVID) Field Descriptions Field Value Description 31-0 4483 0105h Peripheral Revision General-Purpose Input/Output (GPIO) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 933: Gpio Interrupt Per-Bank Enable Register (Binten)
Bank 0 interrupt enable is used to disable or enable the bank 0 interrupts (events from GP0[15-0]). Bank 0 interrupts are disabled. Bank 0 interrupts are enabled. SPRUH82C – April 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 934: Gpio Direction Registers (Dirn)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-1 LEGEND: R/W = Read/Write; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 935: Gpio Bank 8 Direction Register (Dir8)
Direction of pin GPk[j]. The GPkPj bit is used to control the direction (output = 0, input = 1) of pin j in GPIO bankk. GPk[j] is an output. GPk[j] is an input. SPRUH82C – April 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 936: Gpio Output Data Registers (Out_Datan)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 937: Gpio Bank 8 Output Data Register (Out_Data8)
The GPkPj bit is ignored when GPk[j] is configured as an input. GPk[j] is driven low. GPk[j] is driven high. SPRUH82C – April 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 938: Gpio Set Data Registers (Set_Datan)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 939: Gpio Bank 8 Set Data Register (Set_Data8)
GPIO bankk. The GPkPj bit is ignored when GPk[j] is configured as an input. Reading the GPkPj bit returns the output drive state of GPk[j]. No effect. GPk[j] is set to output logic high. SPRUH82C – April 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 940: Gpio Clear Data Registers (Clr_Datan)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 941: Gpio Bank 8 Clear Data Register (Clr_Data8)
GPIO bankk. The GPkPj bit is ignored when GPk[j] is configured as an input. Reading the GPkPj bit returns the output drive state of GPk[j]. No effect. GPk[j] is set to output logic low. SPRUH82C – April 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 942: Gpio Input Data Registers (In_Datan)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 LEGEND: R = Read only; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 943: Gpio Bank 8 Input Data Register (In_Data8)
Status of pin GPk[j]. Reading the GPkPj bit returns the state of pin j in GPIO bank k. GPk[j] is logic low. GPk[j] is logic high. SPRUH82C – April 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 944: Gpio Set Rising Edge Interrupt Registers (Set_Ris_Trign)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 945: Gpio Bank 8 Set Rise Trigger Register (Set_Ris_Trig8)
No effect. Interrupt is caused by a low-to-high transition on GPk[j]. SPRUH82C – April 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 946: Gpio Clear Rising Edge Interrupt Registers (Clr_Ris_Trign)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 947: Gpio Bank 8 Clear Rise Trigger Register (Clr_Ris_Trig8)
GPk[j]. Therefore, this bit will be one in both registers if the function is enabled, and zero in both registers if the function is disabled. No effect. No interrupt is caused by a low-to-high transition on GPk[j]. SPRUH82C – April 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 948: Gpio Set Falling Edge Interrupt Registers (Set_Fal_Trign)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 949: Gpio Bank 8 Set Rise Trigger Register (Set_Fal_Trig8)
No effect. Interrupt is caused by a high-to-low transition on GPk[j]. SPRUH82C – April 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 950: Gpio Clear Falling Edge Interrupt Registers (Clr_Fal_Trign)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 951: Gpio Bank 8 Clear Rise Trigger Register (Clr_Fal_Trig8)
No effect. No interrupt is caused by a high-to-low transition on GPk[j]. SPRUH82C – April 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 952: Gpio Interrupt Status Registers (Intstatn)
LEGEND: R/W = Read/Write; W1C = Write 1 to clear bit (writing 0 has no effect); -n = value after reset General-Purpose Input/Output (GPIO) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 953: Gpio Bank 8 Interrupt Status Register (Intstat8)
Write a 1 to the GPkPj bit to clear the status bit; a write of 0 has no effect. No pending interrupt on GPk[j]. Pending interrupt on GPk[j]. SPRUH82C – April 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 954: Host Port Interface (Hpi)
This chapter describes the host port interface (HPI)..........................Topic Page ..................... 21.1 Introduction ..................... 21.2 Architecture ......................21.3 Registers Host Port Interface (HPI) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 955: Introduction
Memory-mapped peripheral identification register (PID) • Bus holders on host data and address buses (these are actually external to HPI module) SPRUH82C – April 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 956: Functional Block Diagram
HPIA type HCNTL1 Logic Increment high UHPI_HAS HPIC UHPI_HR/W Chip select UHPI_HCS Data UHPI_HDS1, UHPI_HDS2 strobes UHPI_HINT Ready UHPI_HRDY Host Port Interface (HPI) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 957: Industry Standard(S) Compliance Statement
Logic used to communicate between the HPI and the DMA system that moves data to and from memory. This is independent of the EDMA system on the processor processor Entire system-on-chip SPRUH82C – April 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 958: Architecture
When the HPI drives UHPI_HRDY high, the HPI is not ready for the current host cycle to complete. Host Port Interface (HPI) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 959: Pin Multiplexing And General-Purpose I/O Control Blocks
When the GPIO_DIR2.HASZ bit is cleared to 0, configuring the UHPI_HAS pin as an input, writing to the GPIO_DAT2.HASZ bit has no effect. Reading from this bit will return the value on the UHPI_HAS pin. SPRUH82C – April 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 960: Protocol Description
HPID read cycle to an HPID write cycle, or conversely). Otherwise, the memory location accessed by the HPI DMA logic might not be the location intended by the host. Host Port Interface (HPI) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 961: Example Of Host-Processor Signal Connections
Data strobe1 UHPI_HDS1 Data strobe UHPI_HDS2 Data UHPI_HD[15:0] Ready UHPI_HRDY UHPI_HINT Interrupt Data strobing options are given in Section 21.2.6.4 SPRUH82C – April 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 962 HPID, the HPI DMA logic reads the memory address from HPIAW and transfers the data from HPID to the addressed memory location. Host Port Interface (HPI) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 963: Hpi Strobe And Select Logic
Connect the strobe pin to UHPI_HDS1 or UHPI_HDS2, and connect the other strobe pin to logic-level 0. The UHPI_HR/W signal could be driven by a host address line in this case. SPRUH82C – April 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 964: Access Types Selectable With The Uhpi_Hcntl Signals
HPIC. Host Port Interface (HPI) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 965: Multiplexed-Mode Host Read Cycle
FIFO, transitions on UHPI_HRDY may or may not occur. For more information, Section 21.2.6.9. SPRUH82C – April 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 966: Multiplexed-Mode Host Write Cycle
FIFO, transitions on UHPI_HRDY may or may not occur. For more information, Section 21.2.6.9. Host Port Interface (HPI) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 967: Multiplexed-Mode Single-Halfword Hpic Cycle (Read Or Write)
The following sections describe the behavior of UHPI_HRDY during HPI register accesses. In all cases, the chip select signal, UHPI_HCS, must be asserted for UHPI_HRDY to go low. SPRUH82C – April 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 968: Uhpi_Hrdy Behavior During An Hpic Or Hpia Read Cycle In The Multiplexed Mode
UHPI_HCS UHP_HAS UHPI_HCNTL[1:0] UHPI_HR/W HHWIL Internal UHPI_HSTRB 1st halfword 2nd halfword 1st halfword 2nd halfword 1st halfword UHPI_HD[15:0 UHPI_HRDY Host Port Interface (HPI) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 969: Uhpi_Hrdy Behavior During An Hpic Write Cycle In The Multiplexed Mode
UHPI_HCS UHPI_HAS UHPI_HCNTL[1:0] UHPI_HR/W UHPI_HHWIL Interna HSTRB 1st halfword 2nd halfword 1st halfword 2nd halfword 1st halfword UHPI_HD[15:0] UHPI_HRDY SPRUH82C – April 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 970: Uhpi_Hrdy Behavior During A Data Write Operation In The Multiplexed Mode (Case 3: Autoincrementing Selected, Fifo Not Empty Before Write)
UHPI_HCS UHPI_HAS UHPI_HCNTL[1:0] UHPI_HR/W UHPI_HHWIL Internal HSTRB 1st halfword 2nd halfword 1st halfword 2nd halfword 1st halfword UHPI_HD[15:0] UHPI_HRDY Host Port Interface (HPI) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 971: Fifos In The Hpi
Read FIFO Burst reads Host reads Host read HPI DMA pointer write pointer Read FIFO control logic SPRUH82C – April 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 972 As soon as the host activates a read cycle without autoincrementing, prefetching activity ceases until the occurrence of a FETCH command or an autoincrement read cycle. Host Port Interface (HPI) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 973 A nonautoincrement write cycle always should be preceded by the initialization of HPIAW or by another nonautoincrement access, so that the write FIFO is flushed beforehand. SPRUH82C – April 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 974 (internal HSTRB is held high), the FIFOs are held in reset, and host transactions are held off with an inactive UHPI_HRDY signal. Host Port Interface (HPI) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 975: Reset Considerations
7. Release the HPI logic from reset by clearing the HPIRST bit in HPIC. The HPI is now ready to perform data transactions. SPRUH82C – April 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 976: Interrupt Support
Writes of 0 have no effect. A hardware reset immediately clears DSPINT and thus clears an active host-to- CPU interrupt. Host Port Interface (HPI) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 977: Edma Event Support
For detailed information on power management procedures using the PSC, see the Power and Sleep Controller (PSC) chapter. SPRUH82C – April 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 978: Emulation Considerations
Section 21.3.8 HPIAW Host Port Interface Write Address Register Section 21.3.9 HPIAR Host Port Interface Read Address Register Section 21.3.10 Host Port Interface (HPI) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 979: Revision Identification Register (Revid)
0, the SOFT bit selects the HPI mode. The SOFT bit selects the HPI mode. The HPI runs free regardless of the SOFT bit. SPRUH82C – April 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 980: Gpio Enable Register (Gpio_En)
Enable as GPIO for UHPI_HCS, UHPI_HDS1, UHPI_HDS2, UHPI_HR/W pins. Disable pins for GPIO. Pins functions as HPI signal. Enable pins for GPIO. Host Port Interface (HPI) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 981: Gpio Direction 1 Register (Gpio_Dir1)
Table 21-11. GPIO Data 1 Register (GPIO_DAT1) Field Descriptions Field Value Description 31-16 Reserved Reserved 15-0 Data read from/written to UHPI_HDn pin. SPRUH82C – April 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 982: Gpio Direction 2 Register (Gpio_Dir2)
UHPI_HCS pin is an output. HASZ Direction control for UHPI_HAS pin. UHPI_HAS pin is an input. UHPI_HAS pin is an output. Host Port Interface (HPI) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 983: Gpio Data 2 Register (Gpio_Dat2)
Data read from/written to UHPI_HDS1 pin. HCSZ Data read from/written to UHPI_HCS pin. HASZ Data read from/written to UHPI_HAS pin. SPRUH82C – April 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 984: Host Port Interface Control Register (Hpic)
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset Host Port Interface (HPI) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 985: Host Port Interface Control Register (Hpic) Field Descriptions
Halfword ordering bit. HWOB affects both data and address transfers. HWOB must be initialized before the first data or address register access. First halfword is most significant. First halfword is least significant. SPRUH82C – April 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 986: Host Port Interface Write Address Register (Hpiaw)
Table 21-16. Host Port Interface Read Address Register (HPIAR) Field Descriptions Field Value Description 31-0 HPIAR 0-FFFF FFFFh Host port interface read address. Host Port Interface (HPI) SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 987: Inter-Integrated Circuit (I2C) Module
Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1..........................Topic Page ..................... 22.1 Introduction ..................... 22.2 Architecture ....................... 22.3 Registers 1002 SPRUH82C – April 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 988: Introduction
The combined format in 10-bit addressing mode (the I2C sends the slave address the second byte every time it sends the slave address the first byte). Inter-Integrated Circuit (I2C) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 989: Functional Block Diagram
22.1.4 Industry Standard(s) Compliance Statement The I2C peripheral is compliant with the Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1. SPRUH82C – April 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 990: Architecture
Figure 22-2. Multiple I2C Modules Connected TI device Pull-up resistors controller Serial data (I2Cx_SDA) Serial clock (I2Cx_SCL) TI device EPROM Inter-Integrated Circuit (I2C) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 991: Clock Generation
The I2C module must be operated with a prescaled module clock frequency of 6.7 to 13.3 MHz. The I2C prescaler register (ICPSC) must be configured to this frequency range. SPRUH82C – April 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 992: Clock Synchronization
(high) are not fixed and depend on the associated power supply level. See your device-specific data manual for more information. Inter-Integrated Circuit (I2C) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 993: Start And Stop Conditions
(including the MST, STT, and STP bits). Figure 22-6. I2C Peripheral START and STOP Conditions I2Cx_SDA I2Cx_SCL START STOP condition (S) condition (P) SPRUH82C – April 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 994: Serial Data Formats
= The number of data bits (from 1 to 8) specified by the bit count (BC) field of ICM DR. Inter-Integrated Circuit (I2C) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 995: I2C Peripheral 10-Bit Addressing Format With Master-Transmitter Writing To Slave-Receiver (Fdf = 0, Xa = 1 In Icmdr)
= The number of data bits (from 1 to 8) specified by the bit count (BC) field of ICMDR. SPRUH82C – April 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 996: Operating Modes
(XSMT = 0 in ICSTR) after data has been transmitted. Inter-Integrated Circuit (I2C) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 997: Nack Bit Generation
• If STP = 0, make STP = 1 to generate a STOP condition. • Reset the peripheral (IRS = 0 in ICMDR). SPRUH82C – April 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 998: Arbitration
I2Cx_SCL Device #1 lost arbitration and switches off Data from device #1 Data from device #2 Bus line I2Cx_SDA Inter-Integrated Circuit (I2C) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 999: Reset Considerations
Once the bus is determined to be available (the bus is not busy), the I2C is ready to proceed with the desired communication. SPRUH82C – April 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 1000: Interrupt Support
If there is more than one pending interrupt flag, reading ICIVR clears the highest-priority interrupt flag. 1000 Inter-Integrated Circuit (I2C) Module SPRUH82C – April 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...

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