Texas Instruments AM1808 User Manual page 150

AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
CLKS
CLKR
FSR (int)
FSR (ext)
DR
CLKX
FSX (int)
FSX (ext)
FSX (XDATDLY=00b)
DX
A. No. 13 applies to the first data bit only when XDATDLY ≠ 0.
Table 6-65. Timing Requirements for McBSP0 FSR When GSYNC = 1 (see
NO.
1 t Setup time, FSR high before CLKS high
su(FRH-CKSH)
2 t Hold time, FSR high after CLKS high
h(CKSH-FRH)
Table 6-66. Timing Requirements for McBSP1 FSR When GSYNC = 1 (see
NO.
1 t Setup time, FSR high before CLKS high
su(FRH-CKSH)
2 t Hold time, FSR high after CLKS high
h(CKSH-FRH)
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
150 Peripheral Information and Electrical Specifications
1
2
3 3
4 4
5
7
2
3 3
9
11
10
12
Bit 0
Figure 6-32. McBSP Timing
CLKS
Figure 6-33. FSR Timing When GSYNC = 1
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6
8
Bit(n1) (n2)
13 (A)
14
13 (A)
Bit(n1) (n2)
1.3V, 1.2V
MIN MAX MIN
4 4.5
4
1.3V, 1.2V
MIN MAX MIN
5
4
1
2
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AM1808
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(n3)
(n3)
Figure 6-33)
1.1V 1.0V
MAX MIN MAX
5
4 4
Figure 6-33)
1.1V 1.0V
MAX MIN MAX
5 10
4 4
UNIT
ns
ns
UNIT
ns
ns