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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
DDR2/mDDR Memory Controller
DDR_D[0:7]
DDR_DQM[0]
DDR_DQS[0]
DDR_BA[0:2]
DDR_A[0:13]
DDR_CLKP
DDR_CLKN
DDR_CS
DDR_CAS
DDR_RAS
DDR_WE
DDR_CKE
DDR_DQM1
DDR_DQS1
DDR_D[8:15]
DDR_ZP
DDR_DQGATE0
DDR_DQGATE1
DDR_VREF
Terminator, if desired. See terminator comments.
T
(1) See
Figure 6-23
for DQGATE routing specifications.
(2) For DDR2, one of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. For mDDR,
these capacitors can be eliminated completely.
(3) VREF applies in the case of DDR2 memories. For mDDR, the DDR_VREF pin still needs to be connected to the divider circuit.
Figure 6-17. DDR2/mDDR Dual-Memory High Level Schematic
112
Peripheral Information and Electrical Specifications
NC
T
T
T
T
T
T
T
T
T
NC
(1)
T
T
(2)
(2)
0.1 F
0.1 F
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Product Folder Links:
ODT
DQ0 - DQ7
T
BA0-BA2
A0-A13
DM
T
DQS
T
DQS
CK
CK
CS
CAS
RAS
WE
CKE
VREF
BA0-BA2
A0-A13
CK
CK
CS
CAS
RAS
WE
CKE
DM
T
DQS
T
DQS
DQ0 - DQ7
T
ODT
(3)
VREF
(2)
0.1 F
Copyright © 2010–2014, Texas Instruments Incorporated
AM1808
www.ti.com
DDR_DVDD18
0.1 F
1 K
1%
VREF
1 K
1%
0.1 F
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