Table of Contents
Advertisement
www.ti.com
6.25.3 HPI Electrical Data/Timing
Table 6-112. Timing Requirements for Host-Port Interface [1.3V, 1.2V, 1.1V]
NO.
1
t
Setup time, select signals
su(SELV-HSTBL)
2
t
Hold time, select signals
h(HSTBL-SELV)
3
t
Pulse duration, UHPI_HSTROBE active low
w(HSTBL)
4
t
Pulse duration, UHPI_HSTROBE inactive high between consecutive accesses
w(HSTBH)
9
t
Setup time, selects signals valid before UHPI_HAS low
su(SELV-HASL)
10
t
Hold time, select signals valid after UHPI_HAS low
h(HASL-SELV)
11
t
Setup time, host data valid before UHPI_HSTROBE high
su(HDV-HSTBH)
12
t
Hold time, host data valid after UHPI_HSTROBE high
h(HSTBH-HDV)
Hold time, UHPI_HSTROBE high after UHPI_HRDY low. UHPI_HSTROBE
13
t
should not be inactivated until UHPI_HRDY is active (low); otherwise, HPI writes
h(HRDYL-HSTBH)
will not complete properly.
16
t
Setup time, UHPI_HAS low before UHPI_HSTROBE low
su(HASL-HSTBL)
17
t
Hold time, UHPI_HAS low after UHPI_HSTROBE low
h(HSTBL-HASH)
(1) UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR
UHPI_HDS2)] OR UHPI_HCS.
(2) M=SYSCLK2 period in ns.
(3) Select signals include: HCNTL[1:0], HR/W and HHWIL.
Copyright © 2010–2014, Texas Instruments Incorporated
(3)
valid before UHPI_HSTROBE low
(3)
valid after UHPI_HSTROBE low
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links:
AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
(1) (2)
1.3V, 1.2V, 1.1V,
1.0V
MIN
5
2
15
2M
5
2
5
2
2
5
2
AM1808
UNIT
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
211
Advertisement
Table of Contents
