Texas Instruments AM1808 User Manual page 189

Arm microprocessor
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BYTE ADDRESS
0x01E2 326C
0x01E2 3270
0x01E2 3274
0x01E2 3278
0x01E2 327C
0x01E2 3280
0x01E2 3284
0x01E2 3288
0x01E2 328C
BYTE ADDRESS
ACRONYM
0x01E2 2000
0x01E2 2004
SOFTRESET
0x01E2 200C
INTCONTROL
0x01E2 2010
C0RXTHRESHEN
0x01E2 2014
0x01E2 2018
0x01E2 201C
C0MISCEN
0x01E2 2020
C1RXTHRESHEN
0x01E2 2024
0x01E2 2028
0x01E2 202C
C1MISCEN
0x01E2 2030
C2RXTHRESHEN
0x01E2 2034
0x01E2 2038
0x01E2 203C
C2MISCEN
0x01E2 2040
C0RXTHRESHSTAT EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Status Register
0x01E2 2044
C0RXSTAT
0x01E2 2048
C0TXSTAT
0x01E2 204C
C0MISCSTAT
0x01E2 2050
C1RXTHRESHSTAT EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Status Register
0x01E2 2054
C1RXSTAT
0x01E2 2058
C1TXSTAT
0x01E2 205C
C1MISCSTAT
0x01E2 2060
C2RXTHRESHSTAT EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Status Register
0x01E2 2064
C2RXSTAT
0x01E2 2068
C2TXSTAT
0x01E2 206C
C2MISCSTAT
0x01E2 2070
C0RXIMAX
0x01E2 2074
C0TXIMAX
0x01E2 2078
C1RXIMAX
0x01E2 207C
C1TXIMAX
0x01E2 2080
C2RXIMAX
0x01E2 2084
C2TXIMAX
Copyright © 2010–2014, Texas Instruments Incorporated
Table 6-95. EMAC Statistics Registers (continued)
ACRONYM
FRAME65T127
FRAME128T255
FRAME256T511
FRAME512T1023
FRAME1024TUP
NETOCTETS
RXSOFOVERRUNS
RXMOFOVERRUNS
RXDMAOVERRUNS
Table 6-96. EMAC Control Module Registers
REGISTER DESCRIPTION
REV
EMAC Control Module Revision Register
EMAC Control Module Software Reset Register
EMAC Control Module Interrupt Control Register
EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Enable Register
C0RXEN
EMAC Control Module Interrupt Core 0 Receive Interrupt Enable Register
C0TXEN
EMAC Control Module Interrupt Core 0 Transmit Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Enable Register
C1RXEN
EMAC Control Module Interrupt Core 1 Receive Interrupt Enable Register
C1TXEN
EMAC Control Module Interrupt Core 1 Transmit Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable Register
C2RXEN
EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register
C2TXEN
EMAC Control Module Interrupt Core 2 Transmit Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 0 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Status Register
EMAC Control Module Interrupt Core 1 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 1 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Status Register
EMAC Control Module Interrupt Core 2 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 2 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status Register
EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond Register
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Product Folder Links:
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
REGISTER DESCRIPTION
Transmit and Receive 65 to 127 Octet Frames Register
Transmit and Receive 128 to 255 Octet Frames Register
Transmit and Receive 256 to 511 Octet Frames Register
Transmit and Receive 512 to 1023 Octet Frames Register
Transmit and Receive 1024 to 1518 Octet Frames Register
Network Octet Frames Register
Receive FIFO or DMA Start of Frame Overruns Register
Receive FIFO or DMA Middle of Frame Overruns Register
Receive DMA Start of Frame and Middle of Frame Overruns Register
Peripheral Information and Electrical Specifications
AM1808
AM1808
189

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