Texas Instruments AM1808 User Manual page 121

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Figure 6-23 shows the routing for the DQGATE net class.
NO. PARAMETER
1 DQGATE Length F
2 Center to center DQGATE to any other trace spacing
3 DQS/D nominal trace length
(3)
4 DQGATE Skew
(1) CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.
(2) w = PCB trace width as defined in
(3) Skew from CKB0B1
6.11.3.12 MDDR/DDR2 Boundary Scan Limitations
Due to DDR implementation and timing restrictions, it was not possible to place boundary scan cells
between core logic and the IO like boundary scan cells for other IO. Instead, the boundary scan cells are
tapped-off to the DDR PHY and there is the equivalent of a multiplexer inside the DDR PHY which selects
between functional and boundary scan paths.
The implication for boundary scan is that the DDR pins will not support the SAMPLE function of the output
enable cells on the DDR pins and this is a violation of IEEE 1149.1. Full EXTEST and PRELOAD
capability is still available.
Copyright © 2010–2014, Texas Instruments Incorporated
A1
F
A1
Figure 6-23. DQGATE Routing
Table 6-36. DQGATE Routing Specification
Table 6-27.
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SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
Table 6-36 contains the routing specification.
T
T
MIN
CKB0B
(2)
4w
DQLM-50 DQLM
Peripheral Information and Electrical Specifications
AM1808
AM1808
TYP MAX UNIT
(1)
DQLM+50 Mils
100 Mils
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