Texas Instruments AM1808 User Manual page 95

Arm microprocessor
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Table 6-13. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
EDMA0 Channel
EDMA1 Channel
Controller 0
Controller 0
BYTE ADDRESS
BYTE ADDRESS
0x01C0 2208
0x01E3 2208
0x01C0 2210
0x01E3 2210
0x01C0 2218
0x01E3 2218
0x01C0 2220
0x01E3 2220
0x01C0 2228
0x01E3 2228
0x01C0 2230
0x01E3 2230
0x01C0 2238
0x01E3 2238
0x01C0 2240
0x01E3 2240
0x01C0 2250
0x01E3 2250
0x01C0 2258
0x01E3 2258
0x01C0 2260
0x01E3 2260
0x01C0 2268
0x01E3 2268
0x01C0 2270
0x01E3 2270
0x01C0 2278
0x01E3 2278
0x01C0 2280
0x01E3 2280
0x01C0 2284
0x01E3 2284
0x01C0 2288
0x01E3 2288
0x01C0 228C
0x01E3 228C
0x01C0 2290
0x01E3 2290
0x01C0 2294
0x01E3 2294
0x01C0 4000 -
0x01E3 4000 -
0x01C0 4FFF
0x01E3 4FFF
Table 6-14. EDMA3 Transfer Controller (EDMA3TC) Registers
EDMA0
EDMA0
Transfer Controller Transfer Controller Transfer Controller
0
BYTE ADDRESS
BYTE ADDRESS
0x01C0 8000
0x01C0 8400
0x01C0 8004
0x01C0 8404
0x01C0 8100
0x01C0 8500
0x01C0 8120
0x01C0 8520
0x01C0 8124
0x01C0 8524
0x01C0 8128
0x01C0 8528
0x01C0 812C
0x01C0 852C
0x01C0 8130
0x01C0 8530
0x01C0 8140
0x01C0 8540
0x01C0 8240
0x01C0 8640
0x01C0 8244
0x01C0 8644
0x01C0 8248
0x01C0 8648
0x01C0 824C
0x01C0 864C
0x01C0 8250
0x01C0 8650
0x01C0 8254
0x01C0 8654
0x01C0 8258
0x01C0 8658
0x01C0 825C
0x01C0 865C
0x01C0 8260
0x01C0 8660
Copyright © 2010–2014, Texas Instruments Incorporated
ACRONYM
ECR
Event Clear Register
ESR
Event Set Register
CER
Chained Event Register
EER
Event Enable Register
EECR
Event Enable Clear Register
EESR
Event Enable Set Register
SER
Secondary Event Register
SECR
Secondary Event Clear Register
IER
Interrupt Enable Register
IECR
Interrupt Enable Clear Register
IESR
Interrupt Enable Set Register
IPR
Interrupt Pending Register
ICR
Interrupt Clear Register
IEVAL
Interrupt Evaluate Register
QER
QDMA Event Register
QEER
QDMA Event Enable Register
QEECR
QDMA Event Enable Clear Register
QEESR
QDMA Event Enable Set Register
QSER
QDMA Secondary Event Register
QSECR
QDMA Secondary Event Clear Register
Parameter RAM (PaRAM)
EDMA1
1
0
BYTE ADDRESS
0x01E3 8000
0x01E3 8004
0x01E3 8100
0x01E3 8120
0x01E3 8124
0x01E3 8128
0x01E3 812C
0x01E3 8130
0x01E3 8140
0x01E3 8240
0x01E3 8244
0x01E3 8248
0x01E3 824C
0x01E3 8250
0x01E3 8254
0x01E3 8258
0x01E3 825C
0x01E3 8260
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SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
REGISTER DESCRIPTION
ACRONYM
REGISTER DESCRIPTION
PID
Peripheral Identification Register
TCCFG
EDMA3TC Configuration Register
TCSTAT
EDMA3TC Channel Status Register
ERRSTAT
Error Status Register
ERREN
Error Enable Register
ERRCLR
Error Clear Register
ERRDET
Error Details Register
ERRCMD
Error Interrupt Command Register
RDRATE
Read Command Rate Register
SAOPT
Source Active Options Register
SASRC
Source Active Source Address Register
SACNT
Source Active Count Register
SADST
Source Active Destination Address Register
SABIDX
Source Active B-Index Register
SAMPPRXY
Source Active Memory Protection Proxy Register
SACNTRLD
Source Active Count Reload Register
SASRCBREF
Source Active Source Address B-Reference Register
SADSTBREF
Source Active Destination Address B-Reference
Register
Peripheral Information and Electrical Specifications
AM1808
AM1808
95

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