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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
Table 3-7. External Memory Interface A (EMIFA) Terminal Functions (continued)
SIGNAL
NAME
EMA_A[22] / MMCSD0_CMD /
PRU1_R30[30] / GP4[6]
EMA_A[21] / MMCSD0_DAT[0] /
PRU1_R30[29] / GP4[5]
EMA_A[20] / MMCSD0_DAT[1] /
PRU1_R30[28] / GP4[4]
EMA_A[19] / MMCSD0_DAT[2] /
PRU1_R30[27] / GP4[3]
EMA_A[18] / MMCSD0_DAT[3] /
PRU1_R30[26] / GP4[2]
EMA_A[17] / MMCSD0_DAT[4] /
PRU1_R30[25] / GP4[1]
EMA_A[16] / MMCSD0_DAT[5] /
PRU1_R30[24] / GP4[0]
EMA_A[15] / MMCSD0_DAT[6] /
PRU1_R30[23] / GP5[15] / PRU1_R31[23]
EMA_A[14] / MMCSD0_DAT[7] /
PRU1_R30[22] / GP5[14] / PRU1_R31[22]
EMA_A[13] /PRU0_R30[21] / PRU1_R30[21]
/ GP5[13] / PRU1_R31[21]
EMA_A[12] / PRU1_R30[20] / GP5[12] /
PRU1_R31[20]
EMA_A[11] / PRU1_R30[19] / GP5[11] /
PRU1_R31[19]
EMA_A[10] / PRU1_R30[18] / GP5[10] /
PRU1_R31[18]
EMA_A[9] / PRU1_R30[17] / GP5[9]
EMA_A[8] / PRU1_R30[16] / GP5[8]
EMA_A[7] / PRU1_R30[15] / GP5[7]
EMA_A[6] / GP5[6]
EMA_A[5] / GP5[5]
EMA_A[4] / GP5[4]
EMA_A[3] / GP5[3]
EMA_A[2] / GP5[2]
EMA_A[1] / GP5[1]
EMA_A[0] / GP5[0]
EMA_BA[0] / GP2[8]
EMA_BA[1] / GP2[9]
EMA_CLK / PRU0_R30[5] / GP2[7] /
PRU0_R31[5]
EMA_SDCKE / PRU0_R30[4] / GP2[6] /
PRU0_R31[4]
EMA_RAS / PRU0_R30[3] / GP2[5] /
PRU0_R31[3]
EMA_CAS / PRU0_R30[2] / GP2[4] /
PRU0_R31[2]
EMA_CS[0] / GP2[0]
EMA_CS[2] / GP3[15]
EMA_CS[3] / GP3[14]
EMA_CS[4] / GP3[13]
EMA_CS[5] / GP3[12]
EMA_A_RW / GP3[9]
22
Device Overview
(1)
(2)
TYPE
PULL
GROUP
NO.
A10
O
CP[18]
B10
O
CP[18]
A11
O
CP[18]
C10
O
CP[18]
E11
O
CP[18]
B11
O
CP[18]
E12
O
CP[18]
C11
O
CP[19]
A12
O
CP[19]
D11
O
CP[19]
D13
O
CP[19]
B12
O
CP[19]
C12
O
CP[19]
D12
O
CP[19]
A13
O
CP[19]
B13
O
CP[20]
E13
O
CP[20]
C13
O
CP[20]
A14
O
CP[20]
D14
O
CP[20]
B14
O
CP[20]
D15
O
CP[20]
C14
O
CP[20]
C15
O
CP[16]
A15
O
CP[16]
B7
O
CP[16]
D8
O
CP[16]
A16
O
CP[16]
A9
O
CP[16]
A18
O
CP[16]
B17
O
CP[16]
A17
O
CP[16]
F9
O
CP[16]
B16
O
CP[16]
D10
O
CP[16]
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AM1808
POWER
DESCRIPTION
(3)
B
B
B
B
B
B
EMIFA address bus
B
B
B
B
B
B
B
B
B
B
EMIFA address bus
B
B
B
B
B
B
B
B
EMIFA bank address
B
B
EMIFA clock
B
EMIFA SDRAM clock enable
B
EMIFA SDRAM row address strobe
B
EMIFA SDRAM column address strobe
B
EMIFA SDRAM Chip Select
B
B
EMIFA Async Chip Select
B
B
B
EMIFA Async Read/Write control
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