Mmu Instruction Effective Page Number Register - Motorola MPC823e Reference Manual

11.6.1.4 MMU INSTRUCTION EFFECTIVE PAGE NUMBER REGISTER. The MMU
instruction effective page number (MI_EPN) register contains the effective address to be
loaded into a TLB entry.
MI_EPN
BIT 0 1 2
FIELD
RESET
R/W
ADDR
BIT 16 17 18
FIELD EPN
RESET —
R/W R/W
ADDR
NOTE: — = Undefined.
EPN—Effective Page Number for the TLB Entry
This field is the effective address default value of the last instruction TLB miss.
Bits 20–21 and 23–27—Reserved
These bits are reserved and must be set to 0. Ignores on write and returns a 0 on read.
EV—TLB Entry Valid Bit
This bit is set to 1 on every instruction TLB miss.
0 = The TLB entry is invalid.
1 = The TLB entry is valid.
ASID—Address Space ID
This field represent the address space ID of the instruction TLB entry to be compared with
the CASID field of the M_CASID register.
MOTOROLA
3 4 5 6 7
EPN
0
R/W
SPR 787
19 20 21 22 23
RESERVED EV
— 0
R R/W
SPR 787
MPC823e REFERENCE MANUAL
Memory Management Unit
8 9 10 11 12
24 25 26 27 28
RESERVED
0
R
13 14 15
29 30 31
ASID
0
R/W
11-19