Protection - Motorola MPC823e Reference Manual

A successful TLB hit occurs if the incoming effective address matches the EPN stored in a
valid TLB entry and the CASID value stored in the M_CASID register matches the entry's
ASID field. At the same time, the subpage validity flag is set for the subpage pointed to by
the incoming effective address. If a hit is detected, the content of the real page number is
concatenated with the appropriate number of least-significant bits from the effective address
to form the real address that is then sent to the cache and memory system.

11.3 PROTECTION

Access control is assigned on a page-by-page basis and any further manipulation is
conducted on a group basis.
32-BIT EFFECTIVE
CASID
(FROM M_CASID)
MSRPR
TRANSLATION LOOKASIDE BUFFER
32-ENTRY FULLY ASSOCIATIVE ARRAY
REAL PAGE NUMBER
TRANSLATION
ENABLED
32-BIT REAL ADDRESS
Figure 11-1. Block Diagram of Effective-to-Real Address Translation For 4K Pages
MOTOROLA
ADDRESS
20
12
32-BIT LOGICAL
PAGE BYTE
ADDRESS
20
20 12
GROUP NUMBER
BYTE
PROTECTION
TRANSLATION
LOOKUP
ENABLED
TABLE
MPC823e REFERENCE MANUAL
Memory Management Unit
IMPLEMENTATION SPECIFIC
TLB MISS INTERRUPTS
TO CORE
PAGE PROTECTION
FREE ACCESS
PROTECTION
IMPLEMENTATION
SPECIFIC
NO ACCESS
ERROR INTERRUPTS
TO CORE
EXCEPTION
LOGIC
11-3