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register. (Table 3.14.1 shows an example for the case that a 12.5 MHz oscillation is used.)
Table 3.14-1 Operating Frequency Combinations Depending on whether the Clock Doubler Function is
Enabled or Disabled
GCR
CHC
Gear
Divide-
1/1
by-two
1/2
1/4
1/8
(*1)
3
PLL *
-
1/1
1/2
1/4
1/8
1/1
1/2
1/4
1/8
*1
*1
*1
*1: Fixed to 1/1 regardless of settings
*2: To disable the clock doubler function, switch the clock to the divide-by-two clock in advance.
*3: When the PLL oscillation frequency is changed, the clock must be switched to the divide-by-
two clock.
PLL
Clock
oscillation
doubler
frequency
(MHz)
OFF
OFF
OFF
OFF
ON
50.0
OFF
25.0
OFF
25.0
OFF
25.0
OFF
25.0
OFF
12.5
OFF
12.5
OFF
12.5
OFF
12.5
OFF
50.0
ON
25.0
ON
12.5
ON
3.14 Clock Doubler Function
Internal
External
operating
bus
frequency
frequency
(MHz)
(MHz)
6.25
6.25
3.12
3.12
1.56
1.56
0.78
0.78
6.25
3.12
50.0
50.0
25.0
25.0
12.5
12.5
6.25
6.25
3.12
3.12
12.5
12.5
6.25
6.25
3.12
3.12
1.56
1.56
50.0
25.0
25.0
12.5
12.5
6.25
Remarks
Initial value
Inhibited
*2
107
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