Interrupts - Fujitsu Semiconductor Controller MB89950/950A Hardware Manual

F2mc-8l 8-bit microcontroller
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3.4

Interrupts

The MB89950/950A series has 12 interrupt request inputs corresponding to peripheral
functions. The interrupt level can be set independently.
If an interrupt request output is enabled in the peripheral function, an interrupt request
from a peripheral function is compared with the interrupt level in the interrupt
controller. The CPU performs interrupt operation according to how the interrupt is
accepted. The CPU wakes up from standby mode, and returns to the interrupt or normal
operation.
I Interrupt requests from peripheral functions
Table 3.4-1 "Interrupt request and interrupt vector" lists the interrupt requests corresponding to the
peripheral functions. On acceptance of an interrupt, execution branches to the interrupt processing routine.
The contents of interrupt the vector table address corresponding to the interrupt request specifies the branch
destination address for the interrupt processing routine.
An interrupt processing level can be for each interrupt request in the interrupt level setting registers (ILR1,
ILR2, ILR3). Three levels are available.
If an interrupt request with the same or lower level occurs during execution of an interrupt processing
routine, the latter interrupt is not normally processed until the current interrupt processing routine
completes. If interrupt request set the same level occur simultaneously, the highest priority is IRQ0.
Table 3.4-1 Interrupt request and interrupt vector
IRQ0 (External interrupt 0)
IRQ1 (External interrupt 1)
IRQ2 (8-bit PWM timer)
IRQ3 (PWC)
IRQ4 (UART)
IRQ5 (8-bit serial I/O)
IRQ6 (Timebase timer)
IRQ7 (Unused)
IRQ8 (Unused)
IRQ9 (Unused)
IRQA (Unused)
IRQB (Unused)
*1: This priority is applied when interrupts of the same level occur simultaneously.
Interrupt request
Vector table address
Upper
Lower
FFFA
FFFB
H
H
FFF8
FFF9
H
H
FFF6
FFF7
H
H
FFF4
FFF5
H
H
FFF2
FFF3
H
H
FFF0
FFF1
H
H
FFEE
FFEF
H
H
FFEC
FFED
H
H
FFEA
FFEB
H
H
FFE8
FFE9
H
H
FFE6
FFE7
H
H
FFE4
FFE5
H
H
CHAPTER 3 CPU
Bit names of the
interrupt level
Priority
setting register
L01, L00
L11, L10
L21, L20
L31, L30
L41, L40
L51, L50
L61, L60
L71, L70
L81, L80
L91, L90
LA1,LA0
LB1, LB0
(*1)
High
Low
35

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