Control Signal Routing Guidelines; Table 39. Control Signal Routing Guidelines - Intel 852GM Design Manual

System Memory Design Guidelines (DDR-SDRAM)
7.3.5.2.

Control Signal Routing Guidelines

Table 39. Control Signal Routing Guidelines

Signal Group
Motherboard Topology
Reference Plane
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Minimum Spacing to Trace Width Ratio
Minimum Isolation Spacing to non-DDR Signals
Package Length P1
Trace Length L1 – GMCH Control Signal Ball to SO-DIMM Pad
Trace Length L2 – SO-DIMM Pad to Parallel Termination
Resistor Pad
Parallel Termination Resistor (Rt)
Maximum Recommended Motherboard Via Count Per Signal
Length Matching Requirements
NOTES:
1. Recommended resistor values and trace lengths may change in a later revision of the design guide.
2. Power distribution vias from Rt to Vtt are not included in this count.
3. It is possible to route using 2 vias if one via is shared that connects to the SO-DIMM pad and parallel
termination resistor.
4. The overall maximum and minimum length to the SO-DIMM must comply with clock length matching
requirements.
102
Parameter Routing Guidelines
SCKE[3:0], SCS#[3:0]
Point-to-Point with Parallel Termination
Ground Referenced
55 Ω ±15%
Inner layers: 4 mils
Outer layers: 5 mils
2 to 1 (e.g. 8 mil space to 4 mil trace)
20 mils
500 mils ± 250 mils
(See Table 40 for exact package lengths.)
Min = 0.5 inches
Max = 5.5 inches
Max = 2.0 inches
56 Ω ± 5%
6
CTRL to SCK/SCK# [5:0]
See length matching Section 7.3.5.3 and Figure 51.
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Intel 852GM Chipset Platform Design Guide
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