Clock Length Matching Requirements; Clock Reference Lengths - Intel 852GM Design Manual

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3. Exceptions to the trace width and spacing geometries are allowed in the breakout region in order to fan-out the
interconnect pattern. Reduced spacing should be avoided as much as possible.
7.3.3.1.

Clock Length Matching Requirements

The GMCH chipset provides three differential clock pair for each SO-DIMM. A differential clock pair
is made up of a SCK signal and its complement signal SCK#. Refer to Section 7.1 for more details on
length matching requirements.
The differential pairs for one SO-DIMM are:
SCK[0] / SCK#[0]
SCK[1] / SCK#[1]
The differential pairs for the second SO-DIMM are:
SCK[3] / SCK#[3]
SCK[4] / SCK#[4]
The two sets of differential clocks must be length tuned on the motherboard such that any pair to pair
package length variation is tuned out. The three pairs associated with SO-DIMM0 are tuned to a fixed
overall length, including package, and the three pairs associated with SO-DIMM1 are tuned to a fixed
overall length.
The two traces associated with each clock pair are length matched within the package, however some
additional compensation may be required on the motherboard in order to achieve the ± 10 mil length
tolerance within the pair.
Between clock pairs the package length varies substantially. Therefore, the motherboard length of each
clock pair must be length adjusted to tune out package variance. The total length including package
should be matched to within ± 25 mils of each other, as shown in the Figure 44 on the following page.
This may result in a clock length variance of as much as 700 mils on the motherboard.
The first step in determining the routing lengths for clocks and all other clock relative signal groups is to
establish the target length for each SO-DIMM clock group. These target lengths are shown as X0 and
X1, in Figure 44. These are the lengths to which all clocks within the corresponding group will be
matched, and the reference length values used to calculate the length ranges for the other signal groups.
7.3.3.2.

Clock Reference Lengths

The clock reference length for each SO-DIMM clock group is determined by first determining the
longest total clock length required to complete the clock routing. A table of clock package lengths is
provided in Table 34 to assist in this calculation. Once the longest total length is determined for each
clock group, this becomes a lower bound for the associated clock reference length. At this point it is
helpful to have completed a test route of the SDQ/SDQS bus such that final clock reference lengths can
be defined with consideration of the impact on SDQ/SDQS bus routability. Some iteration may be
required.
Once the reference lengths X0 & X1 are defined then the next step is to tune each clock pairs's
motherboard trace segment lengths as required such that the overall length of each clock equals the
associated clock reference length plus or minus the 25-mil tolerance. Again, the reference length for the
two sets of clocks should be offset by the nominal routing length between SO-DIMM connectors.
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Intel 852GM Chipset Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM)
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