Source Synchronous - Address Group; Table 16. Fsb Source Synchronous Data Signal Routing Guidelines; Table 17. Processor Fsb Address Source Synchronous Signal Trace Length Mismatch Mapping - Intel 852GM Design Manual

Intel Celeron M Processor Front Side Bus Design Guidelines

Table 16. FSB Source Synchronous Data Signal Routing Guidelines

Data
Group #1
D[15:0]#
DINV0#
DSTBN[0]# DSTBN[1]# DSTBN[2]# DSTBN[3]#
DSTBP[0]# DSTBP[1]# DSTBP[2]# DSTBP[3]#
NOTES:
1. These data signals can be routed with 2:1 spacing if using 55 ± 10% nominal impedance. However, spacing to
associated strobes must still be kept at 3:1.
5.4.4. Source Synchronous – Address Group
Source synchronous address signals operate at 200 MHz. Thus, their routing requirements are very
similar to the data signals. Refer to Sections 5.4 and 5.4.1 for further details. Table 17 details the
partition of the address signals into matched length groups. Due to the lower operating frequency of the
address signals, pad-to-pin length matching is relaxed to ± 200 mils. Each group is associated with only
one strobe signal. To maximize setup/hold time margin, the address strobes should be trace length
matched to the average trace length of the address signals of their associated group. In addition, each
address signal should be trace length matched within ± 200 mils of its associated strobe signal.

Table 17. Processor FSB Address Source Synchronous Signal Trace Length Mismatch Mapping

CPU Signal Name
REQ[4:0]#, A[16:3]#
A[31:17]#
NOTES:
1. ADSTB[1:0]# should be should be trace length matched to the average length of their associated Address
signals group
2. Each Address signal should be trace length matched to its associated Address Strobe within ± 200 mils.
3. Note that all length matching formulas are based on GMCH die-pad to processor pin total length per signal
group. Package length table are provided for all signals in order to facilitate this pad to pin matching.
Table 18 lists the source synchronous address signals general routing requirements. They should be
routed to a pin-to-pin length minimum of 0.50 inches and maximum of 6.5 inches. Due to the 200-MHz,
high frequency operation of the address signals, the routing guidelines listed in Table 18 allows for 2:1
spacing for the address signals given a 55 Ω ± 15% characteristic trace impedance except for address
strobe signals. But if space permits, 3:1 spacing is strongly advised for these signals.
60
Signal Names
Data Data Data
Group #2 Group #3 Group #4
D[31:16]# D[47:32]# D[63:48]#
DINV1# DINV2# DINV3#
Signal Strobe Associated With the
Matching
± 200 mils
± 200 mils
Total Trace
Length
Transmission
Line Type
Min
(inches) (inches)
Strip-line 0.5
Strip-line 0.5
Strip-line 0.5
Strip-line 0.5
Strobe to Assoc.
Address Signal
Group
ADSTB0#
ADSTB1#
®
Intel 852GM Chipset Platform Design Guide
Nominal Spacing
Impedance & Width
(Ω) (mils)
Max
5.5 55 ± 15% 3:1
5.5 55 ±15% 3:1
5.5 55 ± 15% 3:1
5.5 55 ±15% 3:1
Notes
Matching
± 200 mils 1,2,3
± 200 mils 1,2,3
R