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A
M_DATA0
RP6G3D
10
M_DATA_R_0
4
5
M_DATA1
RP6G3C
10
M_DATA_R_1
3
6
M_DATA2
M_DATA_R_2
RP6G3A
10
1
8
M_DATA3
M_DATA_R_3
RP6G4D
10
4
5
4
M_DATA4
RP6G1D
10
M_DATA_R_4
4
5
M_DATA5
RP6G1C
10
M_DATA_R_5
3
6
M_DATA6
M_DATA_R_6
RP6G1A
10
1
8
M_DATA7
M_DATA_R_7
RP6G2D
10
4
5
M_DATA8
RP6G4C
10
M_DATA_R_8
3
6
M_DATA9
RP6G4B
10
M_DATA_R_9
2
7
M_DATA10
M_DATA_R_10
RP5G12A 10
8
1
M_DATA11
M_DATA_R_11
RP5G12B 10
7
2
M_DATA12
RP6G2C
10
M_DATA_R_12
3
6
M_DATA13
RP6G2B
10
M_DATA_R_13
2
7
M_DATA14
M_DATA_R_14
RP5G2D
10
4
5
M_DATA15
M_DATA_R_15
RP5G2C
10
3
6
M_DATA16
M_DATA_R_16
RP5G12C 10
6
3
M_DATA17
RP5G12D 10
M_DATA_R_17
3
5
4
M_DATA18
M_DATA_R_18
RP5G9C
10
3
6
M_DATA19
M_DATA_R_19
RP5G9B
10
2
7
M_DATA20
M_DATA_R_20
RP5G2B
10
2
7
M_DATA21
RP5G2A
10
M_DATA_R_21
1
8
M_DATA22
M_DATA_R_22
RP5G3C
10
3
6
M_DATA23
M_DATA_R_23
RP5G3B
10
2
7
M_DATA24
M_DATA_R_24
RP5G9A
10
1
8
M_DATA25
RP5G10D 10
M_DATA_R_25
4
5
M_DATA26
M_DATA_R_26
RP5G10B 10
2
7
M_DATA27
M_DATA_R_27
RP5G10A 10
1
8
M_DATA28
M_DATA_R_28
RP5G3A
10
1
8
M_DATA29
RP5G4A
10
M_DATA_R_29
8
1
M_DATA30
M_DATA_R_30
RP5G4C
10
6
3
2
M_DATA31
M_DATA_R_31
RP5G4D
10
5
4
7
M_DATA[63:0]
7,12,14
M_BS0#
7,12,14
M_BS1#
7,12,14
M_CAS#
7,12,14
M_RAS#
1
7,12,14
M_WE#
A
B
M_DATA32
RP5G11D 10
M_DATA_R_32
4
5
M_DATA33
RP5G11C 10
M_DATA_R_33
3
6
M_DATA34
M_DATA_R_34
RP5G11A 10
1
8
M_DATA35
M_DATA_R_35
RP4G5D
10
4
5
M_DATA36
RP5G6A
10
M_DATA_R_36
8
1
M_DATA37
RP5G6B
10
M_DATA_R_37
7
2
M_DATA38
M_DATA_R_38
RP5G6D
10
5
4
M_DATA39
M_DATA_R_39
RP4G3D
10
4
5
M_DATA40
RP4G5C
10
M_DATA_R_40
3
6
M_DATA41
RP4G5B
10
M_DATA_R_41
2
7
M_DATA42
M_DATA_R_42
RP4G6D
10
4
5
M_DATA43
M_DATA_R_43
RP4G6C
10
3
6
M_DATA44
RP4G3C
10
M_DATA_R_44
3
6
M_DATA45
RP4G3B
10
M_DATA_R_45
2
7
M_DATA46
M_DATA_R_46
RP4G4D
10
4
5
M_DATA47
M_DATA_R_47
RP4G4C
10
3
6
M_DATA48
M_DATA_R_48
RP4G6B
10
2
7
M_DATA49
RP4G6A
10
M_DATA_R_49
1
8
M_DATA50
M_DATA_R_50
RP4G7C
10
3
6
M_DATA51
M_DATA_R_51
RP4G7B
10
2
7
M_DATA52
M_DATA_R_52
RP4G4B
10
2
7
M_DATA53
RP4G4A
10
M_DATA_R_53
1
8
M_DATA54
M_DATA_R_54
RP4G1C
10
3
6
M_DATA55
M_DATA_R_55
RP4G1B
10
2
7
M_DATA56
M_DATA_R_56
RP4G7A
10
1
8
M_DATA57
RP4G8D
10
M_DATA_R_57
4
5
M_DATA58
M_DATA_R_58
RP4G8B
10
2
7
M_DATA59
M_DATA_R_59
RP4G8A
10
1
8
M_DATA60
M_DATA_R_60
RP4G1A
10
1
8
M_DATA61
RP4G2D
10
M_DATA_R_61
4
5
M_DATA62
M_DATA_R_62
RP4G2B
10
2
7
M_DATA63
M_DATA_R_63
RP4G2A
10
1
8
RP5G1D
10
5
4
M_BS0_FR# 11
RP5G1A
10
8
1
M_BS1_FR# 11
RP5G8A
10
8
1
M_CAS_FR# 11
RP5G8D
10
5
4
M_RAS_FR# 11
RP5G8B
10
7
2
M_WE_FR# 11
B
C
D
M_DATA_R_[63:0] 11,12,14
7,12,14
M_AA[12:6]
M_AA12
M_AA11
M_AA10
M_AA9
M_AA8
M_AA7
M_AA6
M_AA3
7,12,14
M_AA3
M_AA0
7,12,14
M_AA0
7
M_CB[7:0]
M_CB7
M_CB6
M_CB5
M_CB4
M_CB3
M_CB2
M_CB1
M_CB0
7
M_DQS[8:0]
M_DQS8
M_DQS7
M_DQS6
M_DQS5
M_DQS4
M_DQS3
M_DQS2
M_DQS1
M_DQS0
7
M_DM[8:0]
M_DM0
M_DM1
M_DM2
M_DM3
M_DM4
M_DM5
M_DM6
M_DM7
M_DM8
Title
DDR Series Termination
Size
Project:
Custom
Date:
Wednesday, January 12, 2005
C
D
E
M_AA_FR_[12:6] 11
M_AA_FR_12
RP5G14B 10
7
2
M_AA_FR_11
RP5G14C 10
6
3
RP5G1C
10
M_AA_FR_10
6
3
RP5G14A 10
M_AA_FR_9
8
1
M_AA_FR_8
RP5G14D 10
5
4
M_AA_FR_7
RP5G7A
10
8
1
RP5G7B
10
M_AA_FR_6
7
2
RP5G7D
10
M_AA_FR_3
5
4
M_AA_FR_3 11
M_AA_FR_0
RP5G1B
10
7
2
M_AA_FR_0 11
M_CB_R7
R5G1
10
RP5G5D
10
M_CB_R6
5
4
M_CB_R5
RP5G5B
10
7
2
M_CB_R4
RP5G5A
10
8
1
M_CB_R3
R5G2
10
RP5G13D 10
M_CB_R2
5
4
M_CB_R1
RP5G13B 10
7
2
M_CB_R0
RP5G13A 10
8
1
M_CB_R[7:0] 11,12,14
M_DQS_R8
RP5G13C 10
6
3
RP4G8C
10
M_DQS_R7
3
6
RP4G7D
10
M_DQS_R6
4
5
M_DQS_R5
RP4G5A
10
1
8
M_DQS_R4
RP5G11B 10
2
7
M_DQS_R3
RP5G10C 10
3
6
RP5G9D
10
M_DQS_R2
4
5
M_DQS_R1
RP6G4A
10
1
8
M_DQS_R0
RP6G3B
10
2
7
M_DQS_R[8:0] 11,12,14
M_DM_R_0
RP6G1B
10
2
7
RP6G2A
10
M_DM_R_1
1
8
RP5G3D
10
M_DM_R_2
4
5
M_DM_R_3
RP5G4B
10
7
2
M_DM_R_4
RP5G6C
10
6
3
RP4G3A
10
M_DM_R_5
1
8
RP4G1D
10
M_DM_R_6
4
5
M_DM_R_7
RP4G2C
10
3
6
M_DM_R_8
RP5G5C
10
6
3
M_DM_R_[8:0] 11,12,14
Document Number
Intel Celeron M / 852GM CRB C26116
Sheet
13
of
E
4
3
2
1
Rev
4.403
51
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