Clock Package Length Table; Clock Routing Example; Table 34. Ddr Clock Package Lengths - Intel 852GM Design Manual

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7.3.3.3.

Clock Package Length Table

The package length data in the table below should be used to tune the motherboard length of each
SCLK/SCLK# clock pair between the GMCH and the associated SO-DIMM socket. Intel recommends
that die-pad to SO-DIMM pin length be tuned to within ± 25 mils in order to optimize timing margins
on the interface.

Table 34. DDR Clock Package Lengths

Package length compensation can be performed on each individual clock output thereby matching total
length on SCK/SCK# exactly, or alternatively the average package length can be used for both outputs
of a pair and length tuning done with respect to the motherboard portion only.
7.3.3.4.

Clock Routing Example

Figure 45 is an example of a board routing for the clock signal group.
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Intel 852GM Chipset Platform Design Guide
Signal
SCLK_0
SCLK#_0
SCLK_1
SCLK#_1
SCLK_2
SCLK#_2
SCLK_3
SCLK#_3
SCLK_4
SCLK#_4
SCLK_5
SCLK#_5
System Memory Design Guidelines (DDR-SDRAM)
Pin Number
AB2
AA2
AC26
AB25
AC3
AD4
AC2
AD2
AB23
AB24
AA3
AB4
Package Length (mils)
1177
1169
840
838
1129
1107
1299
1305
643
656
1128
1146
89