Command Topology 3; Figure 58. Command Routing Topology 3 - Intel 852GM Design Manual

System Memory Design Guidelines (DDR-SDRAM)
7.3.6.8.

Command Topology 3

This topology is recommended when the SO-DIMMS are too close together for the series resistor to be
placed between connectors. In this topology the series resistors are placed behind the second SO-
DIMM.
External trace lengths should be minimized. It is suggested that the parallel termination be placed on
both sides of the board to simplify routing and minimize trace lengths. All internal and external signals
should be ground referenced to keep the path of the return current continuous. Intel recommends that
command signal group be routed on same internal layer.
Intel suggests that the parallel termination (Rt) be placed on both sides of the board to simplify routing
and minimize trace lengths. All internal and external signals should be ground referenced to keep the
path of the return current continuous.
Resistor packs are acceptable for the series and parallel command termination resistors but command
signals can't be placed within the same R-packs as data, strobe or control signals. The diagrams and
tables below depict the recommended topology and layout routing guidelines for the DDR-SDRAM
command signals routing to SO-DIMM0 and SO-DIMM1.

Figure 58. Command Routing Topology 3

GMCH
GMCH
Pin
The command signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within
the DDR group, except clocks and strobes. There should be a minimum of 20 mils of spacing to non-
DDR related signals. Command signals should be routed on inner layers with minimized external trace
lengths.
116
L1
P1
SO-DIMM0 PAD
L2
L4
Rs
L3
SO-DIMM1 PAD
®
Intel 852GM Chipset Platform Design Guide
R
Vtt
Rt