Host Clock Group General Routing Guidelines; Clock To Clock Length Matching And Compensation; Emi Constraints; Table 80. Clock Package Length - Intel 852GM Design Manual

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11.2.1.1.

Host Clock Group General Routing Guidelines

When routing the 100-MHz differential clocks, do not split up the two halves of a differential clock pair
between layers, and route to all agents on the same physical routing layer referenced to ground.
If a layer transition is required, make sure that the skew induced by the vias used to transition between
routing layers is compensated in the traces to other agents.
Do not place vias between adjacent complementary clock traces. Vias placed in one half of a differential
pair must be matched by a via in the other half. Differential vias can be placed within length L1,
between clock driver and Rs, if needed to shorten length L1.
11.2.1.2.

Clock to Clock Length Matching and Compensation

The HCLK pairs to the CPU and GMCH should be matched as close as possible in total length from
CK408 pin to the die-pad of the receiving device. In addition, the L1/L1' segments of all three clock
pairs should be length matched to within ± 10 mils. Pair to pair overall length matching requires
knowledge of the package lengths of various CPUs, and the GMCH, as well as the effective length of
the CPU socket/interposer if used. This information is provided in Table 80.
Once routing lengths are defined for the CPU and GMCH, match the motherboard length of the ITP
clock pair to the motherboard length of the CPU clock pair.

Table 80. Clock Package Length

Mobile Intel Pentium 4 Processor-M / Mobile Intel
Celeron Processor Package Length
Intel Celeron M Processor Package Length
Intel 852GM GMCH Package Length
CPU Socket Equivalent Length
11.2.1.3.

EMI Constraints

Clocks are a significant contributor to EMI and should be treated with care. The following
recommendations can aid in EMI reduction:
• Maintain uniform spacing between the two halves of differential clocks.
• Route clocks on physical layer adjacent to the VSS reference plane only.
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Intel 852GM Chipset Platform Design Guide
Parameter
Platform Clock Routing Guidelines
Length
596 mils
485 mils
1142 mils
157 mils
201