Intel 852GM Design Manual page 245

R
Pin Name
IERR#
INIT#
IGNNE#
LINT0/INTR
LINT1/NMI
PROCHOT#
PSI#
PWRGOOD
RESET#
RSVD (pin
AC1, AF7,
C3, C14, E26,
G1)
SLP#
SMI#
STPCLK#
TEST[3:1]
THERMTRIP#
VCC[71:0]
VCCA[3:0]
VCCP[26:0]
®
Intel 852GM Chipset Platform Design Guide
System Series
Termination
Pull-up/Pull-
down
56 Ω pull-up to
VCCP
56 Ω pull up to
VCCP
330 Ω pull-up to
VCCP
54.9 Ω ± 1% 22.6 Ω ± 1%
pull-up to VCCP from pull-up to
ITP700FLEX
If USING
ITP700FLEX
1 K Ω pull-down
to gnd
(default: no
stuff)
56 Ω pull-up to 56 Ω from pull-
VCCP up to ICH4-M
pin
Connect to
VccCORE
Connect to
Vcc1_8
Connect to
VCCP
Voltage
Translation
IERR# is a 1.05 V signal. Voltage
translation logic and/or series resistor
may be required if used.
R1 = 1.3 K Ω Point-to-point connection to ICH4-M.
Voltage transition circuit is required if
R2 = 330 Ω
connecting to FWH. Signal is T-split
Rs = 330 Ω from the ICH4-M to FWH.
Point-to-point connection to ICH4-M.
Point-to-point connection to ICH4-M.
Point-to-point connection to ICH4-M.
R1 = 1.3 K Ω PROCHOT# is a VCCP signal. This
signal is not used on the CRB. So,
R2 = 330 Ω
voltage translation logic may be
Rs = 330 Ω required if used.
If Voltage Translation is Required:
Driver isolation resistor should be
placed at the beginning of the T-split
to the system receiver.
Can be left as NC, if not used for
IMVP.
Point-to-point connection to ICH4-M,
with resistor placed by the processor.
If ITP700FLEX is Not Used: Point-to-
point connection to GMCH.
If ITP700FLEX is Used: RESET#
connects from processor to GMCH
and then forks out to ITP700 FLEX,
with pull-up and series damping
resistor placed next to ITP.
Route to test points.
Point-to-point connection to ICH4-M.
Point-to-point connection to ICH4-M.
Point-to-point connection to ICH4-M.
For each signal, stuffing option for
pull-down should be provided for
testing purposes. For normal
operation, leave the resistors
unpopulated.
Point-to-point connection to ICH4-M,
with pull-up and series resistors
placed by ICH4-M. THERMTRIP# is a
VCCP signal. If connecting to other
device, voltage translation logic may
be required.
Platform Design Checklist
Notes
245