Voltage Translation Logic; Figure 29. Routing Illustration For Topology 3; Table 27. Layout Recommendations For Topology 3 - Intel 852GM Design Manual

Intel Celeron M Processor Front Side Bus Design Guidelines

Figure 29. Routing Illustration for Topology 3

Table 27. Layout Recommendations for Topology 3

L1 + L2
0.5" – 12.0"
0.5" – 12.0"
5.5.8.

Voltage Translation Logic

A voltage translation circuit or component is required on any signals where the voltage signaling level
between two components connected by a transmission line may cause unpredictable signal quality. The
recommended voltage translation circuit for the platform is shown in Figure 30. The driver isolation
resistor, Rs, is place at the beginning of a transmission line that connects to the first bipolar junction
transistor, Q1. Though the circuit shown in Figure 30 was developed to work with signals that require
translation from a 1.05 V to a 3.3 V voltage level, the same topology and component values, in general,
can be adapted for use with other signals as
3.3 V. Any component value changes or component placement requirements for other signals must be
simulated in order to guarantee good signal quality and acceptable performance from the circuit.
In addition to providing voltage translation between driver and receiver devices, the recommended
circuit also provides filtering for noise and electrical glitches. A larger first-stage collector resistor, R1,
can be used on the collector of Q1, however, it will result in a slower response time to the output falling
edge. In the case of the INIT# signal, resistors with value*s as close as possible to those listed in Figure
30 should be used without exception.
With the low 1.05-V signaling level of the Intel Celeron M Processor Front Side Bus, the voltage
translation circuit provides ample isolation of any transients or signal reflections at the input of transistor
Q1 from reaching the output of transistor Q2. Based on simulation results, the voltage translation circuit
can effectively isolate transients as large as 200 mV and that last as long as 60 ns.
70
CPU ICH4-M
L1
L2
Rs
L3 L4
330 Ω ± 5%
0" – 3.0" 0.5" – 6.0"
330 Ω ± 5%
0" – 3.0" 0.5" – 6.0"
3.3V
3.3V
R1
Q2
Q1
L3
3904
Rs R1
1.3 k Ω ± 5% 330 Ω ± 5%
1.3 k Ω ± 5% 330 Ω ± 5%
well, provided the interface voltage of the receiver is also
®
Intel 852GM Chipset Platform Design Guide
FWH
V_IO_FWH
R2
L4
3904
Transmission Line
R2
Type
Micro-strip
Strip-line
R