Line Termination; Terminating Unused Lan Connect Interface Signals; Intel 82562Et / Intel 82562 Em Guidelines; Guidelines For Intel 82562Et / Intel 82562Em Component Placement - Intel 852GM Design Manual

I/O Subsystem
10.9.1.5.

Line Termination

Line termination mechanisms are not specified for the LAN Connect Interface. Slew rate controlled
output buffers achieve acceptable signal integrity by controlling signal reflection, over/undershoot, and
ringback. A 0- Ω to 33- Ω series resistor can be installed at the driver side of the interface should the
developer have concerns about over/undershoot.
Note: The receiver must allow for any drive strength and board impedance characteristic within the specified
ranges.
10.9.1.6.

Terminating Unused LAN Connect Interface Signals

The LAN Connect Interface on the ICH4-M can be left as a no-connect if it is not used.
10.9.2.

Intel 82562ET / Intel 82562 EM Guidelines

For correct LAN performance, designers must follow the general guidelines outlined in Section 10.9.1.
Additional guidelines for implementing an Intel 82562ET or Intel 82562EM Platform LAN Connect
component are provided below.
10.9.2.1.

Guidelines for Intel 82562ET / Intel 82562EM Component Placement

Component placement can affect signal quality, emissions, and temperature of a board design. This
Section will provide guidelines for component placement.
Careful component placement can:
• Decrease potential problems directly related to electromagnetic interference (EMI), which could
cause failure to meet FCC and IEEE test specifications.
• Simplify the task of routing traces. To some extent, component orientation will affect the
complexity of trace routing. The overall objective is to minimize turns and crossovers between
traces.
Minimizing the amount of space needed for the Ethernet LAN interface is important because all other
interfaces will compete for physical space on a motherboard near the connector edge. As with most
subsystems, the Ethernet LAN circuits need to be as close as possible to the connector. Thus, it is
imperative that all designs be optimized to fit in a very small space.
10.9.2.2.

Crystals and Oscillators

To minimize the effects of EMI, clock sources should not be placed near I/O ports or board edges.
Radiation from these devices may be coupled onto the I/O ports or out of the system chassis. Crystals
should also be kept away from the Ethernet magnetics module to prevent interference of communication.
The retaining straps of the crystal (if they should exist) should be grounded to prevent the possibility
radiation from the crystal case and the crystal should lay flat against the PC board to provide better
coupling of the electromagnetic fields to the board.
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